參數(shù)資料
型號: KMPC870ZT133
廠商: Freescale Semiconductor
文件頁數(shù): 34/84頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 133MHZ 256PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 133MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC875/MPC870 PowerQUICC Hardware Specifications, Rev. 4
4
Freescale Semiconductor
Features
– ECB, CBC, and counter modes
– 128-, 192-, and 256-bit key lengths
— Message digest execution unit (MDEU)
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Master/slave logic, with DMA
– 32-bit address/32-bit data
– Operation at MPC8xx bus frequency
— Crypto-channel supporting multi-command descriptors
Integrated controller managing crypto-execution units
Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
Interrupts
— Six external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Twenty-three internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE
, and RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Several serial DMA (SDMA) channels to support the CPM
— Three parallel I/O registers with open-drain capability
On-chip 16
× 16 multiply accumulate controller (MAC)
— One operation per clock (two-clock latency, one-clock blockage)
— MAC operates concurrently with other instructions
— FIR loop—Four clocks per four multiplies
Four baud-rate generators
— Independent (can be connected to SCC or SMC)
— Allows changes during operation
— Autobaud support option
SCC (serial communication controller)
— Ethernet/IEEE 802.3 standard, supporting full 10-Mbps operation
— HDLC/SDLC
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