參數資料
型號: KMPC880
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁數: 14/92頁
文件大小: 1499K
代理商: KMPC880
MPC885/MPC880 Hardware Specifications, Rev. 3
14
Freescale Semiconductor
Power Supply and Power Sequencing
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (
Ψ
JT
) can be used to determine the junction temperature with a measurement of the
temperature at the top center of the package case using the following equation:
T
J
= T
T
+ (
Ψ
JT
×
P
D
)
where:
Ψ
JT
= thermal characterization parameter
T
T
= thermocouple temperature on top of package
P
D
= power dissipation in package
The thermal characterization parameter is measured per the JESD51-2 specification published by JEDEC using a 40
gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the
package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.
7.6 References
Semiconductor Equipment and Materials International
805 East Middlefield Rd
Mountain View, CA 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications
(Available from Global Engineering Documents)
800-854-7179 or
303-397-7956
JEDEC Specifications
http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
8
Power Supply and Power Sequencing
This section provides design considerations for the MPC885/880 power supply. The MPC885/880 has a core voltage
(V
DDL
) and PLL voltage (V
DDSYN
), which both operate at a lower voltage than the I/O voltage V
DDH
. The I/O
section of the MPC885/880 is supplied with 3.3 V across V
DDH
and V
SS
(GND).
The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, and
MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V greater than V
DDH
. In addition, 5-V tolerant pins
can not exceed 5.5 V and remaining input pins cannot exceed 3.465 V. This restriction applies to power up/down
and normal operation.
One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at
different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the
manner in which different voltages are derived. The following restrictions apply:
V
DDL
must not exceed V
DDH
during power up and power down.
V
DDL
must not exceed 1.9 V, and V
DDH
must not exceed 3.465 V.
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