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參數(shù)資料
| 型號： | KS0165 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Multimedia Audio(波表合成芯片) |
| 中文描述： | 多媒體音響（波表合成芯片） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 83K |
| 代理商： | KS0165 |
KS0165
MULTIMEDIA AUDIO
12/
20
GENERAL DESCRIPTION(Continued
)
The specifications for the synthesizer are as follows:
Architecture
Digital Wavetable Synthesizer
Voices
32
Polyphony
32 Notes Maximum
Multi-Timbral Capability
Up To 16 Parts
Sample Memory
Up To 24 Mbytes of ROM/SRAM/DRAM
Available Sample Sets
2Mx16-bits, 1Mx16-bits, 512Kx16-bits
D/A Converter
16-Bit Linear Serial Converter, All Common Data Formats Supported
Sample Playback Rate
Fixed @ 44.1 kHz
Level And Panning Controls
Separate 16-Bit L&R Volume Controls For Each Voice
Filters
2 Separate 2-Pole Resonant Digital Filters For Each Voice
Data Formats
8- Or 16-Bit Signed Linear Or 8- Or 12-Bit Compressed
Envelopes
Hardware Envelopes For Amplitude and Filters
Effects
Effects Loop Provided For DSP Multiple Effects Processor
Firmware
Sequoia Development Group
Pegasus Synthesizer Firmware
Compatibility
Fully General-MIDI Compliant
Roland MT-32 Sound Set Compatible
S
YSTEM
T
IMING
A
ND
C
ONTROL
All timing is derived from a 16.9344 MHz crystal
oscillator, or an externally generated oscillator of
any frequency up to 33Mhz. However, note that the
internal MIDI UART baud rate is directly
proportional to the system clock rate. At any crystal
frequency other than 16.9344 MHz, the UART
BAUD rate will not be correct
.
S
AMPLE
M
EMORY
I
NTERFACE
Each memory access cycle consists of 3 cycles of
the 16.9344 MHz master clock, or 177.15 nsec.
This is adequate to allow use of 150 nsec ROM,
and 80 nsec DRAM. The memory interface
supports a minimum of one and a maximum of
three memory devices. The device connected to
CAS0 must be a ROM. In general the CPU will
execute entirely out of this ROM, and most, if not
all, synthesizer voices will also be playing primarily
from this ROM,
although entirely RAM-based systems can be
supported with some additional logic. ROM
memory accesses are exploited to allow DRAM
refresh to occur simultaneously with ROM accesses
by executing CAS-before-RAS refresh cycles on all
DRAM banks in parallel with all ROM/SRAM
accesses. For systems with ROM-based samples,
this scheme provides adequate refresh for all
DRAM in the system. For a totally DRAM-based
system, it is necessary to allocate one synthesizer
voice to perform DRAM refresh. For a combined
ROM/DRAM system, as long as at least two voices
are playing samples from ROM at all times,
adequate refresh will be provided automatically,
otherwise one voice must be dedicated to providing
DRAM refresh.
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