參數(shù)資料
型號(hào): KS0658
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Source Driver for TFT LCD(源極TFT LCD驅(qū)動(dòng)器)
中文描述: 源驅(qū)動(dòng)器的TFT液晶顯示器(TFT液晶顯示器源極驅(qū)動(dòng)器)
文件頁(yè)數(shù): 3/15頁(yè)
文件大?。?/td> 102K
代理商: KS0658
384CH SOURCE DRIVER FOR TFT LCD
KS0658
3
PIN DESCRIPTION
Pin Symbol
VDD1
VDD2
VSS1
VSS2
Y1 to Y384
D0<0:5>
D1<0:5>
D2<0:5>
D3<0:5>
D4<0:5>
D5<0:5>
SHL
Pin Name
Logic power supply
Driver power supply
Logic ground
Driver ground
Driver Output
Display data input
Description
2.7V to 3.6V
3.0V to 5.0V
Ground (0V)
Ground (0V)
The D/A converted 64 G/S analog voltage is output
The display data is input with a width of 36 bits, gray scale data (6 bits)
×
6 dots (R,G,B)
DX0: LSB, DX5: MSB
Shift direction
control input
This pin controls the direction of shift register in cascade connection.
The shift direction of the shift register is as follows.
SHL = H: DIO1 input ( Y1
Y384 ), DIO2 output
SHL = L: DIO2 input ( Y384
Y1 ), DIO1 output
SHL = H: Used as the start pulse input pin
SHL = L: Used as the start pulse output pin
SHL = H: Used as the start pulse output pin
SHL = L: Used as the start pulse input pin
Refer to shift clock input of the shift register. The display data is loaded to
the data register at the rising edge of CLK2.
Latches the data register contents as rising edge and transfers it to the D/A
converter. Also, after CLK1 input, clears the internal shift register contents.
After 1 pulse input on start, operates normally. CLK1 input timing refers to
the Relationship between CLK1 start pulse (DIO1,DIO2) and blanking
period of the switching characteristic waveform. (page 9)
Input the
γ
-corrected power supplies from external source.
VDD2 > VGMA1 to VGMA10 > VSS2
Keep gray scale power supply unchanged during the gray scale voltage
output.
The input digital video signal is inverted by two data inversion input,
DATA_INV1 and DATA_INV2.
DIO1
Right shift start
pulse input/output
Left shift start pulse
input/output
Shift clock input
DIO2
CLK2
CLK1
Latch input
VGMA1 to
VGMA10
γ
-corrected power
supplies
DATA_INV1
DATA_INV2
Data inversion input
TEST
Test pin
TEST = L: Normal operation.TEST = H : TEST mode
OP AMP cut-off
This pin is internally pulled-down. < Rpd
30k
>
DOX to 2X
DOX to 2X
DATA-INV1
H
Inversion
X
L
Not Inversion
X
DATA-INV2
H
X
Inversion
L
X
Not Inversion
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