參數(shù)資料
型號(hào)： KS57C0502
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： MICROCONTROLLER
中文描述： 單片機(jī)
文件頁(yè)數(shù)： 195/282頁(yè)
文件大?。?/td> 1966K
代理商： KS57C0502
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KS57C0502/C0504/P0504 MICROCONTROLLER
POWER-DOWN
8–1
8
POWER-DOWN
OVERVIEW
The KS57C0502/C0504 microcontroller has two power-down modes to reduce power consumption: idle and
stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP
instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops
while peripherals and the oscillation source continue to operate normally.
When
RESET
occurs during normal operation or during a power-down mode, a reset operation is initiated and
the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
In stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hardware
components are powered-down. The effect of stop mode on specific peripheral hardware components — CPU,
basic timer, serial I/O, timer/ counters 0, and watch timer — and on external interrupt requests, is detailed in
Table 8–1.
NOTE
Do not use stop mode if you are using an external clock source because X
in
input must be
restricted internally to V
SS
to reduce current leakage.
Idle or stop modes are terminated either by a
RESET
, or by an interrupt with the exception of INT0, which are
enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by
RESET
input,
a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag
are set to "1", power-down mode is released immediately upon entering power-down mode.
When an interrupt is used to release power-down mode, the operation differs depending on the value of the
interrupt master enable flag (IME):
— If the IME flag = "0", program execution is started immediately after the instruction which issues the
request to enter power-down mode. The interrupt request flag remains set to logic one.
— If the IME flag = "1", two instructions are executed after the power-down mode release. Then, the vectored
interrupt is initiated. However, when the release signal is caused by INTK or INTW, the operation is
identical to the IME = 0 condition. That is, a vector interrupt is not generated.
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PDF描述
KS57C0504 RS-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 3.3V; Power: 2W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low Noise; No External Capacitor needed; Efficiency to 83%
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KS57C0504 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MICROCONTROLLER
KS57C21116 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Sams
KS57C21124 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Sams
KS57C21132 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Sams
KS57C21408 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21408/C21418/P21408 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers.
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