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參數(shù)資料
| 型號(hào)： | KS57C0504 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RS-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 3.3V; Power: 2W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 單片機(jī) |
| 文件頁(yè)數(shù)： | 232/282頁(yè) |
| 文件大?。?/td> | 1966K |
| 代理商： | KS57C0504 |
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TIMERS and TIMER/COUNTER
KS57C0502/C0504/P0504 MICROCONTROLLER
11–18
TC0 REFERENCE REGISTER (TREF0)
The TC0 reference register TREF0 is an 8-bit write-only register that is mapped to RAM locations F96H and
F97H. It is addressable by 8-bit RAM control instructions.
RESET
initializes the TREF0 value to 'FFH'.
TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to iden-
tify an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being
used to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency
output source.
During timer/counter operation, the value loaded into the reference register compared to the TCNT0 value.
When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal
the interval or event.
The TREF0 value, together with the TMOD0 clock frequency selection, determines the specific TC0 timer in-
terval. Use the following formula to calculate the correct value to load to the TREF0 reference register:
TC0 timer interval = (TREF0 value + 1)
×
1
TMOD0 frequency setting
( assuming a TREF0 value
≠
0 )
TC0 OUTPUT ENABLE FLAG (TOE0)
The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin.
TOE0 is mapped to RAM location F92H.2 and is addressable by 1-bit read and write instructions.
Bit 3
0
Bit 2
TOE0
Bit 1
0
Bit 0
0
F92H
When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a
RESET
occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled,
timer/counter can continue to output an internally-generated clock frequency, via TOL0, to the serial I/O clock
selector circuit.
TC0 OUTPUT LATCH (TOL0)
TOL0 is the output latch for timer/counter. When the 8-bit comparator detects a correspondence between the
value of the counter register TCNT0 and the reference value stored in the TREF0 buffer, the TOL0 value is
inverted — the latch toggles high-to-low or low-to-high.
Whenever the state of TOL0 is switched, the TC0 signal is output. TC0 output may be directed to the TCLO0
pin at P3.1, or it can be output directly to the serial I/O clock selector circuit as the
SCK
signal.
Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic
zero, along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes
immediately. When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be
read, if necessary.
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| KS57C21124 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Sams |
| KS57C21132 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Sams |
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