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參數(shù)資料
| 型號： | KS57C2016 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4-BIT CMOS Microcontroller(4位微控制器) |
| 中文描述： | 4位CMOS微控制器（4位微控制器） |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 47K |
| 代理商： | KS57C2016 |
KS57C2016 MICROCONTROLLER
PRODUCT SPECIFICATION
September 1996
5–4
ELECTRONICS
S
MSUNG
Table 1. KS57C2016 Pin Descriptions
Pin Name
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable
4-bit input port.
1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are assignable by software to
pins P1.0, P1.1, and P1.2.
Same as port 0
47
48
49
50
SCK
SO
SI
BTCO
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P4.0–P4.3
P5.0–P5.3
I
51
52
53
54
55
56
57
58
59
60
61
62
INT0
INT1
INT2
INT4
TCL0
TCL1
CAP
—
TCLO0
TCLO1
CLO
BUZ
—
—
I/O
I/O
Same as port 0
I/O
4-bit I/O ports. N-channel open-drain output up to
9volts. 1-, 4-, and 8-bit read/write and test is
possible. Ports 4 and 5 can be paired to support 8-bit
data transfer. Pull-up resistors are assignable to
individual pins by mask option.
4-bit I/O ports. Port 6 pins are individually software
configurable as input or output. 1-bit and 4-bit
read/write and test is possible. 4-bit pull-up resistors
are software assignable. Ports 6 and 7 can be paired
to enable 8-bit data transfer.
Same as port 0.
63–66
67–70
P6.0–P6.3
P7.0–P7.3
I/O
71–74
75–78
KS0–KS3
KS4–KS7
P8.0
P8.1
P8.2
P8.3
P9.0–P9.3
P10.0–P10.3
P11.0–P13.3
I/O
79
80
81
82
LCDCK
LCDSY
TCLO2
—
—
—
SEG28–
SEG39
P0.0
I/O
Same as port 0.
84–86
87–90
92–100,
1–3
47
O
Output port for 1-bit data (for use as CMOS driver
only)
Serial I/O interface clock signal
SCK
SO
I/O
I/O
Serial data output
48
P0.1
SI
I/O
Serial data input
49
P0.2
BTCO
I/O
Basic interval timer clock output
50
P0.3
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable. Only INT0 is synchronized with
the system clock.
Quasi-interrupt with detection of rising edges
51–52
P1.0, P1.1
INT2
I
53
P1.2
INT4
I
External interrupt with detection of rising or falling
edges
54
P1.3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KS57C21116 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Sams |
| KS57C21124 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Sams |
| KS57C21132 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Sams |
| KS57C21408 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21408/C21418/P21408 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers. |
| KS57C21418 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The KS57C21408/C21418/P21408 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers. |
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