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參數(shù)資料
| 型號(hào)： | KS57C2408A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4-BIT CMOS Microcontroller(4位微控制器) |
| 中文描述： | 4位CMOS微控制器（4位微控制器） |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 50K |
| 代理商： | KS57C2408A |
KS57C2408A/2416A MICROCONTROLLER
PRODUCT SPECIFICATION
September 1996
7–4
ELECTRONICS
S
MSUNG
Table 1. KS57C2408A/2416A Pin Descriptions
Pin Names
Pin
Type
I/O
Description
Number
(80-QFP)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
40–43
36–39
Share Pin
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P4.0–P4.3
P5.0–P5.3
4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or output.
4-bit pull-up resistors are software assignable.
4-bit input port.
1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are software assignable to pins P1.0,
P1.1, and P1.2.
Same as port 0.
SCK
SO
SI
BTCO
INT0
INT1
INT2
INT4
TCL0
TCL1
I
I/O
Same as port 0.
TCLO0
TCLO1
CLO
BUZ
—
—
4-bit I/O ports. N-channel open-drain output up to 9volts. 1 -,
4-, and 8-bit read/write and test is possible. Ports 4 and 5
can be paired to support 8-bit data transfer. Pull-up resistors
are assignable to individual pins by mask option.
4-bit I/O ports. Port 6 pins are individually software
configurable as input or output. 1-bit and 4-bit read/write and
test is possible. 4-bit pull-up resistors are software
assignable. Ports 6 and 7 can be paired to enable 8-bit data
transfer.
Output port for 1-bit data (for use as CMOS driver only).
P6.0–P6.3
P7.0–P7.3
28–31
32–35
KS0–KS3
KS4–KS7
P8.0–P8.11
O
71–80, 1–2
SEG12–
SEG23
AD0–AD3
AD4–AD5
P3.2
P9.0–P9.3
P10.0–P10.1
CLO
I
Input ports for 1-bit or 4-bit data.
1-bit and 4-bit read and test is possible.
CPU clock output
51–56
I/O
26
BUZ
2, 4, 8, or 16 kHz frequency output for buzzer sound with
4.19 MHz main system clock or 32.768 kHz subsystem
clock.
Crystal, ceramic, or RC oscillator signal for main system
clock. (For external clock input, use X
in
and input X
in
's
reverse phase to X
out
.)
Crystal oscillator signal for subsystem clock. (For external
clock input, use XT
in
and input XT
in
's reverse phase to
XT
out
).
External interrupts. The triggering edge for INT0 and INT1 is
selectable. Only INT0 is synchronized with the system clock.
27
P3.3
X
in
, X
out
—
48, 47
—
XT
in
, XT
out
—
49, 50
—
INT0, INT1
I
16–17
P1.0,
P1.1
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