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參數(shù)資料
| 型號(hào)： | KS57P5404 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4-BIT CMOS Microcontroller(4位微控制器) |
| 中文描述： | 4位CMOS微控制器（4位微控制器） |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 28K |
| 代理商： | KS57P5404 |
Preliminary Datasheet
PAGE
3/46
Product
KS57C5404/P5404
REV. NO.
1
SAMSUNG ELECTRONICS CO., LTD. DOC. NO.:RK8011-05-03
PIN DESCRIPTIONS
Table 1 - 1. KS57C5404/P5404 Pin Descriptions
Pin
Name
Pin
Type
I/O
Description
Share
Pin
INT0
INT1
KS0
KS1
P0.0
P0.1
P0.2
P0.3
4-bit I/O port. 1-bit or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software
and are automatically disabled for output pins. Pins are
individually configurable as input or output.
P1.0
P1.1
P1.2
P1.3
P2.0
I/O
4-bit I/O port. 1-bit or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software
and are automatically disabled for output pins. Pins are
individually configurable as input or output.
1-bit I/O port. 1-bit or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software
and are automatically disabled for output pins.
4-bit I/O ports.
1-, 4-, or 8-bit read/write and test is possible.
Pins are individually configurable as input or output.
Pull-up resistors are assignable to input pins by software
and are automatically disabled for output pins.
The N-Channel open drain or push-pull output can be
selected by software(1-bit unit).
TCL0
TCLO0
CLO
BUZ
I/O
P4.0-P4.3
P5.0-P5.1
P5.2
P5.3
I/O
-
-
SDAT
SCLK
INT0
INT1
I/O
I/O
External interrupts with rising/falling edge detection
External interrupts with rising/falling edge detection
P0.0
P0.1
KS0
KS1
TCL0
TCLO0
CLO
BUZ
I/O
Quasi-interrupt input with falling edge detection
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
I/O
I/O
I/O
I/O
External clock input for timer/counter
Timer/counter clock output
CPU clock output
0.5kHz, 1 kHz, 2 kHz, or 4 kHz frequency output at 4.19
MHz for buzzer sound
8 Bit D/A Converter output
DAO
O
-
SDAT *
SCLK *
V
DD
V
SS
I/O
I/O
-
Serial data Read/Write
Serial clock input
Main power supply
P5.2
P5.3
-
-
Ground
-
RESET
TEST
I
I
Reset signal
Test signal input (must be connected to V
SS
)
Crystal, ceramic oscillator signal for system clock
-
-
X
in
, X
out
-
-
* : SDAT and SCLK is available in OTP version
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