參數(shù)資料
型號: KSZ8001S TR
廠商: Micrel Inc
文件頁數(shù): 37/46頁
文件大小: 0K
描述: TXRX 10/100 LINKMD 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝: 1,000
類型: 收發(fā)器
規(guī)程: MII,RMII,SMII
電源電壓: 1.8V, 3.3V
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 帶卷 (TR)
配用: 576-1620-ND - BOARD EVALUATION FOR KSZ8001L
其它名稱: KSZ8001STR
KSZ8001STR-ND
Micrel
KSZ8001
June 2009
Revision 1.04
42
For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), the following reset circuit
is recommended.
KSZ8001
CPU/FPGA
VCC
C 10uF
R 10K
RST_OUT_n
D1
D2
D1, D2: 1N4148
RST#
Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out
from CPU/FPGA provides warm reset after power up. It is also recommend to power up VDD core voltage earlier
than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
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