參數(shù)資料
型號(hào)： KSZ8001SI
廠商： Micrel Inc
文件頁(yè)數(shù)： 6/46頁(yè)
文件大小： 0K
描述： TXRX 10/100 LINKMD 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝： 30
類(lèi)型： 收發(fā)器
規(guī)程： MII，RMII，SMII
電源電壓： 1.8V, 3.3V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
配用： 576-1620-ND - BOARD EVALUATION FOR KSZ8001L
Micrel
KSZ8001
June 2009
Revision 1.04
14
Receive Clock (RXC)
: For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down, and
auto-negotiation is disabled, the receive clock then operates off the master input clock (X1 or TXC). For 10BASE-T links, the receive
clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle. The KSZ8001
synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the
clock with 10ns setup and hold times.
Transmit Enable
: The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after the
last bit of the packet.
Receive Data Valid
: The KSZ8001 asserts RXDV when it receives a valid packet. Line operating speed and MII mode will
determine timing changes in the following way:
For 100BASE-TX link with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble of
the data packet.
For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “ 5D” and remains
asserted until the end of the packet.
Error Signals
: Whenever the KSZ8001 receives an error symbol from the network, it asserts RXER and drives “1110” (4B) on the
RXD pins. When the MAC asserts TXER, the KSZ8001 will drive “H” symbols (a Transmit Error define in the IEEE 802.3 4B/5B
code group) out on the line to force signaling errors.
Carrier Sense (CRS)
: For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS).
An end-of-stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS if IDLE
symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted. For 10T
links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker.
Collision
: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, then the KSZ8001
asserts its collision signal, which is asynchronous to any clock.
RMII (Reduced MII) Data Interface
RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet PHYs and
Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
It is capable of supporting 10Mb/s and 100Mb/s data rates
A single clock reference is sourced from the MAC to PHY (or from an external source)
It provides independent 2 bit wide (di-bit) transmit and receive data paths
It uses TTL signal levels, compatible with common digital CMOS ASIC processes
RMII Signal Definition
Signal Name
Direction
(with respect to
the PHY)
Direction
(with respect to
the MAC)
Use
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and control
interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transit Enable
TXD[1:0]
Input
Output
Transit Data
RX_ER
Output
Input
(Not Required)
Receive Error
Note:
Unused MII signals, TXD[3:2], TXER need to be tied to GND when RMII is used
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