參數(shù)資料
型號: KSZ8031RNLI TR
廠商: Micrel Inc
文件頁數(shù): 3/43頁
文件大小: 0K
描述: TXRX PHY 10/100 3.3V 24-QFN
標準包裝: 1
類型: PHY 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: RMII
電源電壓: 1.8V,2.5V,3.3V
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應商設備封裝: 24-QFN(4x4)
包裝: 標準包裝
其它名稱: 576-3900-6
Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
11
M9999-082710-1.0
Strapping Options – KSZ8021RNL / KSZ8031RNL
Pin Number
Pin Name
Type
(1)
Pin Function
15
PHYAD[1:0]
Ipd/O
The PHY Address is latched at the de-assertion of reset and is configurable to either
one of the following two values:
Pull-up = PHY Address is set to 00011b (0x3h)
Pull-down (default) = PHY Address is set to 00000b (0x0h)
PHY Address bits [4:2] are set to ‘000’ by default.
23
ANEN_SPEED
Ipu/O
Auto-Negotiation Enable and SPEED mode
Pull-up (default) = Enable Auto-Negotiation and set 100Mbps Speed
Pull-down = Disable Auto-Negotiation and set 10Mbps Speed
At the de-assertion of reset, this pin value is latched into register 0h bit [12] for Auto-
negotiation enable/disable, register 0h bit [13] for the Speed select, and register 4h
(Auto-Negotiation Advertisement) for the Speed capability support.
Note:
1.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pin may drive high/low during
power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with the RMII CRS_DV signal, to be latched to the
unintended high/low states. In this case, an external pull-up (4.7K) or pull-down (1.0K) should be added on the PHYAD[1:0] strap-in pin to ensure
the intended value is strapped-in correctly.
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