參數(shù)資料
型號(hào): KSZ8041NL-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 23/54頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8041NL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8041NL
主要屬性: 單芯片 PHY,10BASE-T/100BASE-TX
次要屬性: MII,RMII,HP 自動(dòng) MDI,MDI-X 自動(dòng)極性校正
已供物品:
產(chǎn)品目錄頁(yè)面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3296-5-ND - IC TXRX PHY 10/100 AUTO 32-MLF
576-2109-6-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-2109-1-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-2109-2-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
KSZ8041NLA3TR-ND - TRANSCEIVER 10/100 32-MLF
576-1645-6-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-1645-1-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-1645-2-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
其它名稱: 576-1621
Micrel, Inc.
KSZ8041NL/RNL
September 2010
3
M9999-090910-1.4
Revision History
Revision
Date
Summary of Changes
1.0
10/13/06
Data sheet created.
1.1
4/27/07
Added maximum MDC clock speed.
Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pull-
downs.
Changed Model Number in Register 3h – PHY Identifier 2.
Changed polarity (swapped definition) of DUPLEX strapping pin.
Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6].
Set “Disable power saving” as the default for Register 1Fh bit [10].
Corrected LED1 (pin 31) definition for Activity in LED mode 01.
Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter.
Added a 100pF capacitor on REXT (pin 10) in Pin Description table.
1.2
7/18/08
Added Automotive Qualified part number to Ordering Information.
Added maximum case temperature.
Added thermal resistance (
θ
JC).
Added chip maximum current consumption.
1.3
12/11/09
Added Automotive Qualified part number, KSZ8041NL EAM, to Ordering Information.
Changed MDIO hold time (min) from 10ns to 4ns.
Added LED drive current.
Renamed Register 3h bits [3:0] to “manufacturer’s revision number” and changed default value to
“Indicates silicon revision.”
Updated RMII output delay for CRSDV and RXD[1:0] output pins.
Added support for Asymmetric PAUSE in register 4h bit [11].
Added control bits for 100Base-TX preamble restore (register 14h bit [7]) and 10Base-T preamble
restore (register 14h bit [6]).
Changed strapping pin definition for CONFIG[2:0] = 100 from “PCS Loopback” to “MII 100Mbps
Preamble Restore.”
Corrected MII timing for tRLAT, tCRS1, tCRS2.
Added KSZ8041RNL device and updated entire data sheet accordingly.
1.4
01/19/10
Removed part number (KSZ8041NL EAM) from Ordering Information.
Removed chip maximum current consumption.
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