參數(shù)資料
型號(hào): KSZ8051MNLI TR
廠(chǎng)商: Micrel Inc
文件頁(yè)數(shù): 14/59頁(yè)
文件大?。?/td> 0K
描述: TXRX PHY 10/T100 3.3V 32QFN
特色產(chǎn)品: KSZ8051/8031/8021 Series
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: MII
電源電壓: 1.8V,2.5V,3.3V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): 576-3901-6
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
21
M9999-070910-1.0
Figure 1. Auto-Negotiation Flow Chart
MII Data Interface (KSZ8051MNL only)
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
10Mbps and 100Mbps data rates are supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 4-bit wide, a nibble.
By default, the KSZ8051MNL is configured to MII mode after it is powered up or hardware reset with the following:
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to ‘000’ (default setting).
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