參數(shù)資料
型號(hào)： KSZ8695X
廠商： Micrel Inc
文件頁(yè)數(shù)： 10/39頁(yè)
文件大小： 0K
描述： IC SWITCH 10/100 5PORT 208PQFP
標(biāo)準(zhǔn)包裝： 24
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 208-MQFP，208-PQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
包裝： 托盤
配用： 576-1624-ND - KIT EVAL KSZ8695X EXPERIMENT
其它名稱： 576-1025
Micrel, Inc.
KS8695X
June 2006
18
M9999-060106
Signal Descriptions by Group
Clock and Reset Pins
Pin
Name
I/O Type
(1)
Description
150
XCLK1/
CPUCLK
I
External Clock In. This signal is used as the source clock for the transmit clock of
the internal MAC and PHY. The clock frequency should be 25MHz ±50ppm. The
XCLK1 signal is also used as the reference clock signal for the internal PLL
togenerate the 125MHz internal system clock.
CPUCLK: factory clock test input when the internal PLL is disabled (factory test
signal).
151
XCLK2
I
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
96
URTSN/
CPUCLKSEL
O/I
Normal Mode: UART request to send. Active low output.
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory test signal): the external clock to the CPUCLK pin is used
as the internal CPU clock source.
148
RESETN
I
KS8695X chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695X. When in the reset state, all the output pins are tri-
stated and all open drain signals are floating.
83
WRSTO
O
Watchdog timer reset output. This signal is asserted for at least 200ms if RESETN
is asserted or when the internal watchdog timer expires.
85
EROEN/
WRSTPLS
O/I
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low.
When asserted, this signal controls the output enable port of the specified device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
JTAG Interface Pins
Pin
Name
I/O Type
(1)
Description
110
TCK
I
JTAG test clock.
111
TMS
I
JTAG test mode select.
112
TDI
I
JTAG test data in.
113
TDO
O
JTAG test data out.
114
TRSTN
I
JTAG test reset. Active low.
WAN Ethernet Physical Interface Pins
Pin
Name
I/O Type
(1)
Description
159
WANRXP
I
WAN PHY receive signal + (differential).
160
WANRXM
I
WAN PHY receive signal – (differential).
162
WANTXM
O
WAN PHY transmit signal – (differential).
163
WANTXP
O
WAN PHY transmit signal + (differential).
158
WANFXSD/
DOUT
I/O
WAN fiber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb fiber mode. DOUT:factory analog test mode.
Note
:
1. I = Input.
O = Output.
I/O = Bidirectional.
O/I = Output in normal mode; input pin during reset.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8695X-EVAL 功能描述:網(wǎng)絡(luò)開發(fā)工具 KSZ8695X Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
KSZ8721B 功能描述:以太網(wǎng) IC 10/100 BASE-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-SSOP (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8721B TR 功能描述:以太網(wǎng) IC 10/100 BASE-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-SSOP (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8721B 制造商:Micrel Inc 功能描述:Transceiver IC 制造商:Micrel Inc 功能描述:IC, TRANSCEIVER, SSOP-48
KSZ8721BA4 功能描述:TXRX 10/100 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,140 系列:AU 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND
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