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參數(shù)資料
| 型號： | KSZ9021RN |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 50/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX 10/100/1000 SGL 48QFN |
| 特色產(chǎn)品： | KSZ9021RN Single-port Gigabit Transceiver |
| 標準包裝： | 260 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
| 配用： | 576-3874-ND - BOARD EVALUATION FOR KSZ9021RN |
| 其它名稱： | 576-3637 KSZ9021RN-ND |
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MCP444X/446X
DS22265A-page 54
2010 Microchip Technology Inc.
6.2
I2C Operation
The MCP44XX’s I2C module is compatible with the
Philips I2C specification. The following lists some of the
modules features:
7-bit slave addressing
Supports three clock rate modes:
- Standard mode, clock rates up to 100 kHz
- Fast mode, clock rates up to 400 kHz
- High-speed mode (HS mode), clock rates up
to 3.4 MHz
Support Multi-Master Applications
General call addressing
Internal weak pull-ups on interface signals
The I2C 10-bit addressing mode is not supported.
The Philips I2C specification only defines the field
types, field lengths, timings, etc. of a frame. The frame
content defines the behavior of the device. The frame
content for the MCP44XX is defined in Section 7.0.
6.2.1
I2C BIT STATES AND SEQUENCE
clock is generated by the master. The following defini-
tions are used for the bit states:
Start bit (S)
Data bit
Acknowledge (A) bit (driven low) /
No Acknowledge (A) bit (not driven low)
Repeated Start bit (Sr)
Stop bit (P)
6.2.1.1
Start Bit
The Start bit (see Figure 6-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
FIGURE 6-2:
Start Bit.
6.2.1.2
Data Bit
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 6-5).
FIGURE 6-3:
Data Bit.
6.2.1.3
Acknowledge (A) Bit
The A bit (see Figure 6-4) is typically a response from
the receiving device to the transmitting device.
Depending on the context of the transfer sequence, the
A bit may indicate different things. Typically the Slave
device will supply an A response after the Start bit and
8 “data” bits have been received. an A bit has the SDA
signal low.
FIGURE 6-4:
Acknowledge Waveform.
Not A (A) Response
The A bit has the SDA signal high. Table 6-1 shows
some of the conditions where the Slave Device will
issue a Not A (A).
If an error condition occurs (such as an A instead of A),
then an START bit must be issued to reset the
command state machine.
TABLE 6-1:
MCP45XX/MCP46XX A / A
RESPONSES
SDA
SCL
S
1st Bit
2nd Bit
SDA
SCL
Data Bit
1st Bit
2nd Bit
Event
Acknowledge
Bit
Response
Comment
General Call
A
Only if GCEN bit is
set
Slave Address
valid
A
Slave Address
not valid
A
Device Mem-
ory Address
and specified
command
(AD3:AD0 and
C1:C0) are an
invalid combi-
nation
A
After device has
received address
and command
Communica-
tion during
EEPROM write
cycle
A
After device has
received address
and command,
and valid condi-
tions for EEPROM
write
Bus Collision
N.A.
I2C Module
Resets, or a “Don’t
Care” if the colli-
sion occurs on the
Master’s “Start bit”
A
8
D0
9
SDA
SCL
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