參數(shù)資料
型號(hào): L4979D13TR
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: LOW DROP VOLTAGE REGULATOR
中文描述: 低壓差穩(wěn)壓器
文件頁(yè)數(shù): 5/10頁(yè)
文件大小: 268K
代理商: L4979D13TR
5/10
L4979MD L4979D
Note:
1. see fig4 (behavior of output current versus regulated voltage Vo)
2. guaranteed by design
3. When Vo becomes lower than 4V, the reset reaction time decreases down to 2
μ
s assuring a faster reset condition in this particular
case.
2
The voltage regulator uses a p-channel MOS transistor as a regulating element. With this structure a low drop-
out voltage at current up to 150mA is achieved. The output voltage is regulated up to transient input supply volt-
age of 40V. No functional interruption due to over-voltage pulses is generated. The high precision of the output
voltage is obtained with a pre-trimmed reference voltage. A short circuit protection to GND is provided.
VOLTAGE REGULATOR
Figure 4. Behavior of output current versus regulated voltage Vo (see a.m. Note 1)
3
The reset circuit monitors the output voltage Vo. If the output voltage drops below V
o_th
then Res becomes low
with a delay time trr. Real trr value changes as a non-linear function of delta (V
o-th
- V
o
). The reset low signal is
guaranteed for an output voltage Vo greater than 1V.
When the output voltage becomes higher than Vo_th then Res goes high with a delay trd. This delay is obtained
by 512 periods of an oscillator (see fig. 5). The oscillator period is given by:
RESET
V
cw
I
cwc
Charge current
V
s
= 13.5V, V
cw
= 0.1V
4
7.5
14
μ
A
V
cw
I
cwd
Discharge current
V
s
= 13.5V, V
cw
= 2.5V
1.0
2.4
4.5
μ
A
V
cw
T
wop
Watchdog period
V
s
= 13.5V, C
tw
= 47nF
25
50
90
ms
R
es
t
wol
Watchdog output low time
V
s
= 13.5V, C
tw
= 47nF
6
10
22
ms
ENABLE
E
n
V
en_l
Enable input low voltage
1
V
E
n
V
en_h
Enable input high voltage
3
V
E
n
V
en_hy
Enable input hysteresis
700
1000
1100
mV
E
n
I
_leak
Pull down current
E
n
= 5V
2
10
20
μ
A
Pin
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vo
Vo_ref
Iout
Ishort Ilim
ELECTRICAL CHARACTERISTICS
(continued)
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