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參數(shù)資料
| 型號： | L4979MD13TR |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | LOW DROP VOLTAGE REGULATOR |
| 中文描述： | 低壓差穩(wěn)壓器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 268K |
| 代理商： | L4979MD13TR |
L4979MD L4979D
6/10
and reset pulse delay trd is given by:
t
rd
= 512 x T
osc
Figure 5. Reset Time Diagram.
4
The watchdog input Wi monitors a connected microcontroller. If pulses are missing, the reset output Res is
set to low. The pulse sequence time can be set within a wide range thorough the external capacitor C
tw
. The
watchdog circuit discharges the capacitor C
tw
with the constant current Icwd. If the lower threshold Vwlth is
reached, a watchdog reset is generated. To prevent this reset, the microcontroller must generate a positive edge
during the discharge of the capacitor before the voltage has reached the threshold V
wlth
. In order to calculate
the minimum time Tdis during which the microcontroller must generate the positive edge, the following equation
can be used:
(V
whth
- V
wlth
) x C
tw
= I
cwd
x T
dis
Each W
i
positive edge switches the current source from discharging to charging; the same happens when the
lower V
wlth
threshold is reached. When the voltage reaches the upper threshold V
whth
the current switches from
charging to discharging. The result is a saw tooth voltage at the watchdog timer capacitor C
tw
.
WATCHDOG
Figure 6. Watchdog time diagram
T
osc
V
--------------------–
V
I
cr
)
C
tr
[
]
V
--------------------–
V
I
dr
)
C
tr
[
]
+
=
trr
< trr
trd = 512 Tosc
Tosc
Vrhth
Vrlth
Res
Vcr
Vo
Wi
Vout_th
Wi
Res
Vcw
Vwlth
Vwhth
twol
Twop
Tdis
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