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參數(shù)資料
| 型號(hào)： | L6245 |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | VOICE COIL MOTOR CONTROLLER, 1.5 A, PQFP64 |
| 封裝： | PLASTC, QFP-64 |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大小： | 1025K |
| 代理商： | L6245 |
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cycle. On a write operation, following write going
low and whatever setup time required to latch
data, data acknwledge is driven low. This notifies
the processor that the cycle can end. This proces-
sor responds by raising write, indicating the end
of the cycle. Data acknowledge must go to high
impedance within 20nsec to clear the bus for the
next cycle.
This handshaking design allows a peripheral to
control the length of the bus cycle. The peripheral
can take as much time as it needs to drive data
onto the bus, then drive DTACK low. Likewise,
the peripheral can wait as long as it needs to set
up data and latch it (or set up data if WR is used
to latch), then drive DTACK low. However, per-
formance is an issue, so even though this control
has been given to the peripheral, it must not be
abused. All delays are minimized to assure opti-
mum system speed, infact the bus can be driven
synchronously (E.G. has regarding DTACK) when
procesor clocks below 12MHz are used.
Figure 1: System Bus Timing (see Table 8)
Table 8: System Bus Timing
Symbol
Description
TAS
Address Setup Time (non MUX bus; (MUX bus)
TCS
System Select to Address Strobe
TASW
Address Strobe Width
TASRD
Address Strobe to RD
TRDDV
RD to Data Driven
TRDDH
Read Data Hold
TRDCS
RD High to CS High
TDVDT
Data Valid to DTACK
TDTRD
DTACK to RD High
TRDDT
RD High to DTACH High
TASWR
Address Strobe to WR
TDVWR
Write Data Valid to WR
TWRDTL
WR to DTACK
TDTWR
DTACK to WR High
TWRCS
WR High to CS High
TWRDT
WR High to DTACK High
TWRDH
Write Data Hold
L6245
12/15
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