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參數(shù)資料
| 型號： | L64020XBC |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP176 |
| 封裝： | PLASTIC, TQFP-176 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 370K |
| 代理商： | L64020XBC |
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L64020 Single Chip DVD Decoder
11
The L64020 has six major interfaces; host, channel, memory, video,
audio, and miscellaneous and test.
Host Interface
BUSMODE
Host Controller Select Pin
Input
This pin must be tied to VSS if the host CPU is an Intel
processor or to VDD if it is a Motorola processor. The
Intel processor uses two separate pins, READn and
WRITEn, for read and write transfers. The Motorola
processor uses a single read/write signal, READ.
CSn
Chip Select
Input
This active-LOW signal indicates an attempt by an
external host CPU to access the L64020 either for a read
or a write bus cycle. CSn must be asserted for the entire
read/write cycle and may be held LOW for more than one
bus transaction.
A[8:0]
Address
Input
Nine-bit address input selects one of 512 internal
registers. The address value on these lines is latched on
the falling edge of READn in a read cycle and on the
falling edge of WRITEn in a write cycle in Intel mode.
Motorola mode uses a separate address strobe, ASn.
ASn
Address Strobe
Input
Active-LOW address strobe input. This signal is used in
Motorola mode to latch the address.
D[7:0]
Host Data Bus
Bidirectional
The host uses the D[7:0] bidirectional data bus to
program the L64020 and access status and bitstream
information during operation. During a read bus cycle,
D[7:0] carries valid information from an internal L64020
register. DTACKn/RDYn or WAITn indicate when the data
on the bus is valid. In write cycles, the data is latched by
the L64020 on the rising edge of DSn/WRITEn.
DSn/WRITEn Data Strobe/Write Strobe
Input
DSn - Motorola Mode
DSn indicates when the host strobes the data in or out of
the L64020. Read transactions start when DSn, CSn, and
ASn are all LOW. During a write cycle, the L64020
latches the data on the bus on the rising edge of DSn.
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