參數(shù)資料
型號(hào)： L64724BC
廠商： LSI CORP
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 32/32頁(yè)
文件大?。?/td> 338K
代理商： L64724BC
L64724 Satellite Receiver
9
PCLK
PLL Clock Output
Output
The L64724’s internal PLL clock synthesis module gener-
ates the PCLK signal. The CLK signal drives the PLL.
The PLL clock synthesis module can be congured to
generate a PCLK rate that is appropriate for all data
rates.
PLLAGND
PLL Analog Ground
Input
PLLAGND is the analog ground pin for the PLL module
and is normally connected to the system ground plane.
PLLVDD
PLL Power
Input
PLLVDD is the power supply pin for the PLL module and
is normally connected to the system power (VDD) plane.
PLLVSS
PLL Ground
Input
PLLVSS is the ground pin for the PLL module and is nor-
mally connected to the system ground plane.
ADC Interface
The ADC module converts the incoming IVIN and QVIN signals into an
internal 6-bit digital representation for processing. The following pins
support the ADC module.
ADCVDDI/Q
ADC Power
Input
ADCVDDI/Q are the analog power supply pins for the
ADC module and are normally connected to the system
power (VDD) plane.
ADCVREFI/Q ADC Reference
Input
ADCVREFI/Q are connected to the ADC reference
voltage.
ADCVREFNI/Q
ADC Reference
Input
ADCVREFNI/Q are connected to the ADC reference
voltage.
ADCVSSI/Q
ADC Analog Ground
Input
ADCVSSI/Q are the analog ground pins for the ADC
module and are normally connected to the system
ground plane.
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L64730GM-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor
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