參數(shù)資料
型號: L6563TR
廠商: 意法半導(dǎo)體
元件分類: 基準電壓源/電流源
英文描述: ADVANCED TRANSITION-MODE PFC CONTROLLER
中文描述: 先進的轉(zhuǎn)型模式PFC控制器
文件頁數(shù): 19/25頁
文件大?。?/td> 362K
代理商: L6563TR
19/25
L6563
Figure 41. Effect of boost inductor saturation on the MOSFET current and detection method
4.7 Power management/housekeeping functions
A special feature of this IC is that it facilitates the implementation of the "housekeeping" circuitry needed
to coordinate the operation of the PFC stage to that of the cascaded DC-DC converter. The functions re-
alized by the housekeeping circuitry ensure that transient conditions like power-up or power down se-
quencing or failures of either power stage be properly handled.
This device provides some pins to do that. As already mentioned, one communication line between the IC
and the PWM controller of the cascaded DC-DC converter is the PWM_LATCH pin, which is normally
open when the PFC works properly and goes high if it loses control of the output voltage (because of a
failure of the control loop) or if the boost inductor saturates, with the aim of latching off the PWM controller
of the cascaded DC-DC converter as well (
Feedback failure protection (FFP)
for more details ).
A second communication line can be established via the disable function included in the PFC_OK pin
(
Feedback failure protection (FFP)
for more details ). Typically this line is used to allow the PWM con-
troller of the cascaded DC-DC converter to shut down the L6563 in case of light load, to minimize the no-
load input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut
down the supply voltage. Interface circuits like those shown in
Figure 42
, where the L6563 works along
with the L5991, PWM controller with standby function, can be used. Needless to say, this operation as-
sumes that the cascaded DC-DC converter stage works as the master and the PFC stage as the slave or,
in other words, that the DC-DC stage starts first, it powers both controllers and enables/disables the op-
eration of the PFC stage.
Figure 42. Interface circuits that let the L5991/ L5991A disable the L6563 at light load (slave PFC)
The third communication line is the PWM_STOP pin (#9), which works in conjunction with the RUN pin
(#10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the
cascaded DC-DC converter. The pin is an open collector, normally open, that goes low if the device is
disabled by a voltage lower than 0.52V on the RUN pin. It is important to point out that this function works
correctly in systems where the PFC stage is the master and the cascaded DC-DC converter is the slave
or, in other words, where the PFC stage starts first, powers both controllers and enables/disables the op-
T
delay
I
L
Multiplier
Output
Vcs
t
1.7V
T
delay
Multiplier
Output
Vcs
t
I
L
1.7V
T
delay
Multiplier
Output
Vcs
t
I
L
1.7V
Inductor not saturating
Inductor slightly saturating
Inductor saturating hard
L5991/A
ST-BY
4
16
27
k
Vref
L6563
PFC_OK
7
100 k
150 k
150 k
47
k
100 nF
BC547
BC547
BC557
L5991/A
ST-BY
4
16
27
k
Vref
L6563
Vcc
14
100 k
150 k
150 k
15
k
100 nF
BC557
BC547
BC557
100 nF
Supply_Bus
相關(guān)PDF資料
PDF描述
L6566A Multi-mode controller for SMPS with PFC front-end
L6566ATR Multi-mode controller for SMPS with PFC front-end
L6566B Multi-mode controller for SMPS
L6566BTR Multi-mode controller for SMPS
L6567 HIGH VOLTAGE DRIVER FOR CFL
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