參數(shù)資料
型號: L6566ATR
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Multi-mode controller for SMPS with PFC front-end
中文描述: 多模式開關(guān)電源控制器,PFC前端
文件頁數(shù): 36/51頁
文件大?。?/td> 410K
代理商: L6566ATR
Application information
L6566A
36/51
Figure 23. OVP function: timing diagram
(pin 4)
The ZCD pin will be connected to the auxiliary winding through a resistor divider R
Z1
, R
Z2
(see
Figure 8 on page 20
). The divider ratio k
OVP
= R
Z2
/ (R
Z1
+ R
Z2
) will be chosen equal
to:
Equation 10
where Vout
OVP
is the output voltage value that is to activate the protection, Ns the turn
number of the secondary winding and Naux the turn number of the auxiliary winding. The
value of R
Z1
will be such that the current sourced by the ZCD pin be within the rated
capability of the internal clamp:
Equation 11
where Vin
max
is the maximum dc input voltage and Ns the turn number of the primary
winding. See
Section 5.2: Zero current detection and triggering block; oscillator block on
page 21
for additional details.
To reduce sensitivity to noise and prevent the latch from being erroneously activated, first
the OVP comparator is active only for a small time window (typically, 0.5 μs) starting 2 μs
after MOSFET’s turn-off, to reject the voltage spike associated to the positive-going edges
of the voltage across the auxiliary winding Vaux; second, to stop the L6566A the OVP
comparator must be triggered for four consecutive switching cycles. A counter, which is
reset every time the OVP comparator is not triggered in one switching cycle, is provided to
this purpose.
t
GD
Vaux
5V
t
t
t
STROBE
t
COUNTER
RESET
t
COUNTER
STATUS
t
0
ZCD
(pin 11)
2 μs
0.5 μs
OVP
t
FAULT
0
0
0
0
1
1
2
2
0
0
1
1
2
2
3
3
4
0
NORMAL OPERATION
TEMPORARY DISTURBANCE
FEEDBACK LOOP FAILURE
t
COUT
Vcc_PFC
(pin 6)
t
Naux
Ns
Vout
5
k
OVP
OVP
=
max
3
1
Z
Vin
Np
Naux
10
3
1
R
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