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參數(shù)資料
| 型號： | L6610D |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 電源管理 |
| 英文描述： | 6-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | SO-24 |
| 文件頁數(shù)： | 14/29頁 |
| 文件大小： | 600K |
| 代理商： | L6610D |
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L6610
4
UNDERVOLTAGE, OVERVOLTAGE, OVERCURRENT DETECTION AND RELEVANT TIMINGS
The IC provides on-board undervoltage and overvoltage protection for 3V3, ±5V, ±12V Main input pins and
Dmon auxiliary input pin. Overcurrent protection is available for 12V and 5V or 3.3V, digitally selectable. The
internal fault logic is illustrated in figure 21.
Figure 21. Simplified Fault logic
– Main inputs overvoltage: whenever one of main outputs (3.3V, ±5V, ±12V) is detected as going over-
voltage, MFAULT is latched high (which stops the Main PWM) and PW-OK goes low. Cycling the PS-
ON switch or reducing Vdd below its undervoltage threshold releases the latch. A delay of 6s is imple-
mented before MFAULT latching.
The OV protection for the 12V and 5V outputs can be disabled (see "On board trimming and mode op-
erating" section).
– Main inputs undervoltage: when an undervoltage on main outputs is detected, MFAULT is latched
high (the Main PWM stops) and PW-OK goes low. The latches are released, by default, cycling the PS-
ON switch or reducing Vdd below its undervoltage threshold (latching mode); optionally, an attempt is
made to restart the supply after of 1 second (bounce mode). The choice depends on the selected mode
(see "On board trimming and mode operating" section).
Debounce logic is implemented for 3.3V and 5V so that an undervoltage condition on these signals has
to last 450s to be recognized as valid while 6s debounce logic is implemented for 12V and -12V input
signal. When all main undervoltages are over and ACsns is OK (see the relevant section), PW_OK goes
high after a delay of 250ms.
– Dmon input overvoltage: whenever the Dmon input pin is detected as going overvoltage, both
MFAULT and DFAULT are latched high. The latch is released by reducing Vdd below its undervoltage
threshold. Debounce logic is implemented so that MFAULT and DFAULT signals are latched only if the
overvoltage condition lasts more than 6s.
To protect the load against overvoltage, typical solutions make use of a power crowbar (SCR) driven by
Delay 1s
In
Clock
Out
Reset
Debounce 75ms
Clock
In
Reset
Out
PS-ON
Restart Mode
Vdd
Vdd_OV
Vdd_UVL
ON
C lock
R eset
UVB 64ms
In
Out
C lock
R eset
UVB 64ms
In
Out
Dmon_UV
Dmon_OV
ACsense
Vref
Main_OC
Main_OV
Reset
Clock
In
Out
Debounce 6
s
Reset
Clock
In
Out
Reset
Clock
In
Out
Latch
R
SQ
Clock
In
Reset
Out
Delay 250ms
Delay 2.5ms
Reset
Out
Clock
In
Vdd
PW-OK
Cout
Latch
R
SQ
Latch
R
SQ
Dfault
Vdd
Mfault
Latch
R
SQ
Vdd
D_UVB
Reset
Clock
In
Out
Reset
Clock
In
Out
+/-12V_Main_UV
+3V3 +/-5V_Main_UV
Debounce 6
s
Debounce 500
s
Debounce 500
s
Debounce 6
s
+
OCP_BOUNCE
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