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參數(shù)資料
| 型號： | L6712QTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, QCC36 |
| 封裝： | 6 X 6 MM, 1 MM HEIGHT, VFQFPN-36 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 624K |
| 代理商： | L6712QTR |
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L6712A L6712
it. The voltage drop due to the output capacitor discharge is given by the following equation:
Where DMAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during
3.11 INDUCTOR DESIGN
The inductance value is defined by a compromise between the transient response time, the efficiency, the
cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation
to maintain the ripple current
IL between 20% and 30% of the maximum output current. The inductance
value can be calculated with this relationship:
Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the con-
verter response time to a load transient. The response time is the time required by the inductor to change
its current from initial to final value. Since the inductor has not finished its charging time, the output current
is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
The response time to a load transient is different for the application or the removal of the load: if during
the application of the load the inductor is charged by a voltage equal to the difference between the input
and the output voltage, during the removal it is discharged only by the output voltage. The following ex-
pressions give approximate response time for
I load transient in case of enough fast compensation net-
work response:
The worst condition depends on the input voltage available and the output voltage selected. Anyway the
worst case is the response time after removal of the load with the minimum output voltage programmed
and the maximum input voltage available.
3.12 MAIN CONTROL LOOP
The system control loop topology depends on the DROOP pin connection: if connected to FB (droop func-
tion active) an Average Current Mode topology must be considered while, if connected to GND (droop
function not active) a Voltage Mode topology must be considered instead.
Anyway, the system control loop encloses the Current Sharing control loop to allow proper sharing to the
inductor' currents. Each loop gives, with a proper gain, the correction to the PWMs in order to minimize
the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the
output voltage control loop fixes the output voltage equal to the reference programmed by VID (with or
without the droop effect and with or without considering the Remote Amplifier Gain). Figure 16 reports the
block diagram of the main control loop.
V
OUT
I
2
OUT
L
4C
OUT
V
In
d
max
V
OUT
–
()
--------------------------------------------------------------------------------
=
L
V
IN
V
OUT
–
fs
I
L
------------------------------
V
OUT
V
IN
---------------
=
t
application
L
I
V
IN
V
OUT
–
------------------------------
t
removal
L
I
V
OUT
---------------
=
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