參數(shù)資料
型號(hào): L6731BTR
廠商: 意法半導(dǎo)體
英文描述: Transistor; Type: Amplifiers/Bipolar; VCEO (V): -25; Ic (A): -1; Pc (W): 0.8; hFE: 85 to 330; VCE (sat) (V) max: -0.5; Package: TO-92Mod
中文描述: 可調(diào)式降壓同步整流專用的DDR控制器內(nèi)存
文件頁(yè)數(shù): 11/24頁(yè)
文件大?。?/td> 311K
代理商: L6731BTR
L6731B
Device description
11/24
5.3
Bypassing the LDO to avoid the voltage drop with low Vcc
If V
CC
5V the internal LDO works in dropout with an output resistance of about 1
. The
maximum LDO output current is about 100mA and so the output voltage drop is 100mV, to
avoid this the LDO can be bypassed.
5.4
Internal and external references
It is possible to set the internal/external reference and the switching frequency by setting the
proper voltage at the DDR-IN pin. The maximum value of the external reference is 2.5V (typ.):
V
EAREF
from 0% to 80% of V
CCDR
-> External reference/F
SW
= 250KHz
V
EAREF
from 80% to 95% of V
CCDR
-> V
REF
= 0.6V/F
SW
=500KHz
V
EAREF
from 95% to 100% of V
CCDR
-> V
REF
= 0.6V/F
SW
=250KHz
Providing an external reference from 0V to 450mV the output voltage will be regulated but
some restrictions must be considered:
The minimum OVP threshold is set at 300mV;
The under-voltage-protection doesn't work;
The PGOOD signal remains low;
To set the resistor divider it must be considered that a 100K pull-down resistor is integrated into
the device (see
Figure 5.
). Finally it must be taken into account that the voltage at the
DDR-IN
pin is captured by the device at the start-up when V
CC
is about 4V.
Figure 4.
Bypassing the LDO
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