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參數(shù)資料
| 型號： | L9311 |
| 英文描述： | Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access |
| 中文描述： | 線路接口和線路接入電路全功能用戶接口高縱向平衡，振鈴繼電器，和GR - 909測試訪問 |
| 文件頁數(shù)： | 12/50頁 |
| 文件大?。?/td> | 852K |
| 代理商： | L9311 |
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Data Sheet
July 2001
Ringing Relay, and GR-909 Test Access
L9311 Full-Feature SLIC with High Longitudinal Balance,
12
Agere Systems Inc.
Operating States
(continued)
Input State Coding
(continued)
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in
when the LATCH control input goes low. Data must be set up 200 ns before LATCH goes low and held 50 ns after
LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, B2, and B3.
The data control inputs at B0, B1, B2, and B3 may only be changed when LATCH is high. NSTAT supervision out-
put is not controlled by the LATCH control input.
Table 2. Primary Control States
Table 3. Secondary Control States
Table 4. Supervision Coding
B3
0
0
0
0
0
0
0
0
X
B2
0
0
0
0
1
1
1
1
X
B1
0
0
1
1
0
0
1
1
X
B0
0
1
0
1
0
1
0
1
X
RESET
1
1
1
1
1
1
1
1
0
State
Scan
Powerup, forward battery
Powerup, reverse battery
Tip and ring amp
Ring
Tip amp
Ring amp
Disconnect, break before make
Disconnect, break before make
B3
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
Active
State
TESTLEV, TESTSIG Tip/Ring voltage
TESTLEV, TESTSIG Tip voltage
TESTLEV, TESTSIG Ring voltage
TESTLEV, TESTSIG VTX
—
current
TESTLEV
TESTLEV, TESTSIG VITR
—
current
—
—
V
REF
Unassigned
TESToff
Pin NSTAT
Pin TRGDET
0 = off-hook or ring trip
1 = on-hook and no ring trip
0 = ring ground
1 = no ring ground
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