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參數資料
| 型號： | L9824 |
| 文件頁數： | 7/11頁 |
| 文件大?。?/td> | 229K |
| 代理商： | L9824 |
TRANSFER FROM POWER OUTPUT TO DATA
OUTPUT.
The opposite signal path (READING MODE) from
theoutputtotheDATAterminalsisused for thedia-
gnosticfunctionto monitortheoutputstatus.Output
voltages greater than 3.5V lead to ”HIGH” stateat
theDATA terminals. TheHIGH level is typical4.5V
andinternally stabilized. For ”LOW” level the satu-
ration voltageof N-Channel MOStransistoris rele-
vant.
SHORT-CIRCUIT PROTECTION.
Fortheuse oflampsa particularshort-currentchar-
acteristicisimplementedanditisdrawn infig.3.Be-
cause of the low resistance of lamps during the
ON-phasethecurrent limit isfortypical2.5msabout
thedoubleasfor thesecondcurrent limiting phase.
Detecting a short circuit condition means that the
channeloutputremains low inany conditionfor the
check time T
CH
= T
TSCH
+ T
SCL
independentof the
statusof theinputs.
Thesetimeperiodsaregeneratedfrom twofrequen-
cies 400Hz/6.4kHzcoming from thecommon oscil-
lator part. If the current limiting is active after the
check periodan overload is recognizedand the re-
garding channelis switched off and theDATA flip-
flop is also reset as explainedearlier.
Inordertosavesupplycurrentaspecialshort-circuit
protection is used that needs no quiescentcurrent
duringthe ON-state as long as no overload is pre-
sent at the output. Because of this special circuit
configuration the output current must exceed a gi-
venthresholdtoactivatethecurrentregulationloop.
ThiscurrentthresholdI
TH
is determinedby the ON-
resistance R
DSON
of the outputDMOS and the mi-
nimumoperatingsupplyvoltageV
Smin
ofthelimiting
circuit and can be easilycalculatedin thefollowing
way:
I
TH
= V
Smin
/R
DSON
= 4V/1.5
= 2.7A (typical value
at T
j
= 25
°
C)
When theoutputis shortedforinstanceto V
S
ama-
ximum peakcurrentwill occurforashortdurationup
to the limiting circuit is switchedon and the settling
time is over. Under worst case conditions (T
j
= –
40
°
C), V
S
= 16V, whereR
DSON
is lowest) the peak
currentcan reach 7A with a duration of 1
μ
s at V
out
= 15Vand 4A with a duration of 20
μ
s at V
out
= 5V.
COMMON PARTS
MODE CONTROL.
Bythe”TRANSFER” and”ENABLE” input, working
modes can be selected as shown in the truthtable
intheupperpartoffig.1.Thecontrolsignalscoming
frombothinputcomparatorswhichdeterminethelo-
gic threshold and hysteresis drive the mode logic
that distributesthe right data to all output blocks.
TRANSFER, HOLD and READ MODE are explai-
nedbefore. The remaining STANDBY MODE swit-
ches the clock oscillator and all outputs off and
reducethequiescentcurrentbelow100
μ
A.Thisme-
ans that only the both mode comparators and the
bandgapregulatorare active.The inputdatastored
beforewill be not changed.
OSCILLATORPART.
The clock oscillator contains an on-chip capacitor
andrequiresthereforenoexternalcomponents.The
oscillation frequency is approximately in the range
of 50kHz.This oscillator signalis devidedbya7 bit-
counterwhich createsthetwofrequenciesfortheti-
ming of all short current control circuits in each
outputblock.
VOLTAGEREFERENCE.
Themainreferencecellisabandgapcontrolledvery
lowdropvoltageregulator.Allthresholdvoltagesfor
the input comparators, the diagnostic comparators
andthethermaloverloadcomparatorsaswellasthe
referencevoltage for theCMOS supplybuffers are
derivedfrom one resistor devider.
Becauseofthelowcurrentcapabilityoftheregulator
two buffers are used to supply the CMOS logic for
every four channels.These voltage followers work
like a current multiplier at a very low quiescentcur-
rent.Aclampingcircuit preventsthattheCMOSbre-
akdownvoltage will be reached.
CURRENT REFERENCE + POWER–ONRESET.
Thetwotemperaturecompensatedcurrentlinesare
generated directly from the bandgap voltage and
are switched off by the mode logic to save supply
current.Athirdunswitchedcurrentlinebiasesthein-
put comparatorsand CMOSbuffers.
During supply voltage rise, power-on reset circuit
providesa definedstatusofall latchesintheCMOS
logic. Froma supplyvoltage of about 4V on it ena-
blesthewholelogic andthedevicecanwork.Below
4ValllatchesaresettoholdtheoutputsintotheOFF
state.
PROTECTIONCIRCUITS
ESD–PROTECTION.
Bothinputcomparators(ENABLE,TRANSFER)are
ESD protectedandinclude zenerdiodesthatclamp
the gatesof theinternalMOSFETs to minimal 15V.
Seconddiodesclamp theseinputsto V
S
if thesup-
ply voltageis lower than 0.6V belowthe zener volt-
age.
L9824
7/11
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