The LA1784M includes two AGC circuits in its front end block.
— Antenna input limiter using a pin diode.
— FET second gate control
The AGC input pin is pin 59, and the AGC circuit turns on when a signal of about 30 mVrms is input.
AGC activation
The pin diode drive circuit turns on when VCC – V2 is greater than or equal to about 1 V, and input limitation is
applied to the antenna circuit. In application circuits, there will be an attenuation of about 30 to 40 dB. Next, when
an adequate current flows in the antenna attenuator pin diode, the inductance falls, the FET second gate voltage
drops, the FET gm falls, and the AGC operates. The recommended FET is the Sanyo 3SK263, which is an
enhancement-type MOSFET. Therefore, full AGC is applied when the voltage, VG2-S, between the second gate and
the source is 0. Note that if a depletion-type MOSFET is used, AGC will not be applied unless VG2-S is less than 0.
No. 6039-26/50
LA1784M
0
1
2
3
4
5
6
7
8
9
–10
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140
fr = 98.0 Hz
VCC = 8 V
Ta = 25
°C
Range where
the AGC does
not operate
AGC level due
to the MOSFET
second gate:
about 35 dB
AGC level
due to the
pin diode:
about 35 dB
V2AGC
—
V
ANT IN — dB
V2 AGC Characteristics
Fig.9
59
64
60
63
62
OSC
A12077
MIX
INPUT
MIX
OUT
MIX
OUT
MIX
INPUT
MIX
V
CC
MIX
Mixer circuit
Mixer
The mixer circuit in this IC is a double-balanced mixer with both
balanced input and balanced output.
Input circuit type
Emitter input
Input impedance: 25
Due to optimized device geometry, emitter current, the bias, this IC
achieves the following performance.
Mixer input usable sensitivity: 15 dB
Mixer input IMQS: 90.5 dB
(For an oscillator level of 200 mVrms)
* The mixer input IMQS is defined as:
fr = 98.8 MHz, no input
fu1 = 98.8 MHz, 1 kHz, 30% modulation
fu2 = 99.6 MHz, no modulation
The interference 1 and 2
input levels such that
generated intermodulation
output signal-to-noise ratio
becomes 30 dB when an
interference signal with the
same level as the mixer input
is input, and distortion occurs
in the mixer.
Fig. 10