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參數(shù)資料
| 型號： | LA2650 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Bass Boost IC |
| 中文描述： | 低音增強集成電路 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 319K |
| 代理商： | LA2650 |
Recommended Data Transfer Procedure
The boost gain select and the left and right channel boost add on/off settings should only be set at power on. During
normal operation, control the device by setting the add level select and boost on/off settings. Using the add level select
and boost on/off settings for control is superior from the standpoint of minimizing switching noise (spikes).
Limiter (ALC) Operation
The level limiter operates when the boost gain amplifier output level reaches about 2 V rms, and suppress further level
increases above that point.
The non-clipping limiter operates to prevent boost gain amplifier output clipping at power-supply voltages (about 8.5 V
and lower) at which the output cannot be amplified to the operating level of the level limiter.
Notes on Control Data
— Data is read in on the rising edge of the clock signal.
— Data consists of 8 bits, D1 through D8.
— The input data is latched on the rising edge of the enable signal.
— When the LA2650 is not being controlled, the clock and the enable signal must be held high.
— Intervals between commands
The timing of the intervals on the enable signal must meet the conditions shown in the figure below.
Initial Settings at Power on
— All data is reset to low when power is first applied.
— Applications should send their initial data settings once the IC is fully operational after power is applied, i.e. about
0.5 second after power is applied.
Data Timing
No. 5652-10/13
LA2650
Timing characteristics
min
typ
max
unit
Enable clock delay time
t
ec
t
dc
t
ch
t
cl
t
ce
t
ck
5
μs
Data clock delay time
5
μs
Clock high-level hold time
5
μs
Clock low-level hold time
5
μs
Clock enable delay time
5
μs
Clock cycle time
10
μs
At least 10 μs
Enable
Enable
Enable
t
ce
t
ch
t
ec
t
dc
t
ck
t
cl
Data
Data
Clock
Clock
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