LA6543M
No. 5904-7/7
This catalog provides information as of December, 1998. Specifications and information herein are subject to change
without notice.
A simplified diagram of VIN and VG is shown below.
1) Consider an 11 k
(typ.) inserted between V
IN and VG.
2) When only VIN and not VG is used, the BTL gain (between VO
+ and VO–) is set to 6 dB (0 dB for AMP only). This also applies for the
case when VIN is not used and an 11 k external resistor is connected to VG for input.
3) Gain is set by the input impedance as seen from point A.
When VG only is used and the external resistor is R, the BTL gain (between VO
+ and VO–) is
20 log (11 k
/R) + 6 dB.
When an 11 k
resistor is inserted between V
IN and VG, and input is via VIN, the combined resistance Rz as seen from point A is
Rz = 5.5 k
. Gain is
20 log (11 k
/5.5 k) + 6 dB = 12 dB.
Gain Setting (input pins and adjustment pins)
This IC incorporates a level shifter circuit. The input references the voltage VREF to be applied and references the
voltage (VSS – VBE (0.7))/2V to be output.
Offset Voltage
PS
VG
VIN
VREF
VREF1
VREF2
VSS
+
–
+
–
AMP2
AMP1
+
–
+
–
11 k
11 k
11 k
GND
VO+
VO–
CH4 only
A
A10997
Level
shift
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