μPD720102 PCI Bus Interface : handles 32-bit 33 MHz PCI bus master and target" />
參數(shù)資料
型號(hào): LA72730-N-E
廠商: ON Semiconductor
文件頁(yè)數(shù): 5/8頁(yè)
文件大小: 0K
描述: IC AUDIO/VIDEO SWITCH TV 24SDIP
標(biāo)準(zhǔn)包裝: 22
功能: 音頻/視頻切換
電路: 1 X 4:1(增強(qiáng)監(jiān)控器)
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V
工作溫度: -20°C ~ 70°C
安裝類(lèi)型: 通孔
封裝/外殼: 24-SDIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 24-SDIP
包裝: 管件
Data Sheet S17998EJ4V0DS
3
μPD720102
PCI Bus Interface
: handles 32-bit 33 MHz PCI bus master and target function which comply with PCI
specification revision 2.2. The number of enabled ports is set by bit in configuration
space.
Arbiter
: arbitrates among two OHCI host controller cores and one EHCI host controller core.
OHCI Host Controller
: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling.
EHCI Host Controller
: handles high- (480 Mbps) signaling.
Root Hub
: handles USB hub function in host controller and controls connection (routing) between
host controller core and port.
PHY
: consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,
etc.
INTA0
: is the PCI interrupt signal for OHCI Host Controller.
SMI0
: is the interrupt signal which is specified by open host controller interface specification
for USB release 1.0a and enhanced host controller interface specification revision 1.0.
The SMI signal of each OHCI host controller and EHCI host controller appears at this
signal.
PME0
: is the interrupt signal which is specified by PCI-bus power management interface
specification revision 1.1. Wakeup signal of each host controller core appears at this
signal.
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