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參數(shù)資料
| 型號(hào)： | LA73026AV |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO44 |
| 封裝： | 0.275 INCH, SSOP-44 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 264K |
| 代理商： | LA73026AV |
LA73026AV
No.A0239-10/13
Transfer data format
The transfer data is composed by START condition, Slave address data
*3, and STOP condition.
After setting up the START condition, please transfer the Slave Address (regulated as “10010100” in SW IC). Group
and next control data (Please see “Data structure”)
Slave Address is composed by 7bits, and this bit 8th bit
*4 should be set as [0].
But SW IC is not equipped with such a data out function, please keep this bit as [0].
The both of Group data and control data are composed by 8bits, and the one control action is defined with combination
of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by sending some
control data together.
The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. But LA73026AV
adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data . If you want to stop
transfer action, please transfer the STOP condition without fail.
*3 There are 3 control groups.
*4 This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept mode
with SW IC) and [1] means accept mode (send mode with SW IC) fundamentally.
Data structure
START condition
Slave Address
R/W ACK Group ACK
Control data
ACK
…
STOP condition
Initialize
SW IC is initialized as the following mode for circuit protection. Please see “Sub address and data byte table” on page 9.
Characteristics of the SDA and SCL 1/0 stages for SW IC
Parameter
Symbol
Min
Max
Unit
LOW level input voltage
VIL
0
1.0
V
HIGH level input voltage
VIH
2.0
5.0
V
LOW level output current
IOL
3.0
mA
SCL clock frequency
fSCL
100
kHz
Set-up time for a repeated START condition
tSU: STA
4.7
s
Hold time START condition. After this period, the first clock pulse is generated.
tHD: STA
4.0
s
LOW period of the SCL clock
tLOW
4.7
s
Rise time of both SDA and SDL signals
tR
0
1.0
s
HIGH period of the SCL clock
tHIGH
4.0
s
Fall time of both SDA and SDL signals
tF
0
1.0
s
Data hold time
tHD: DAT
0
s
Data set-up time
tSU: DAT
250
ns
Set-up time for STOP condition
tSU: STO
4.0
s
BUS free time between a STOP and START condition
tBUF
4.7
s
Definition of timing
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