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參數資料
| 型號： | LA75505M |
| 文件頁數： | 7/13頁 |
| 文件大小： | 224K |
| 代理商： | LA75505M |
No. 6930-7/13
LA75505M
Continued from preceding page.
Continued on next page.
Pin No.
Pin
Pin Function
Internal Circuit
Pin 4 is the video output pin.
The EQ amplifier can be thought of as shown
below.
4
5
VIDEO-OUT
EQ-OUT
output
Time
constant switch
output
Pin 6 is the PLL detector APC filter pin.
Normally the following are used:
R = 330
C1 = 0.47 μ to 1 μF
C2 = 100 pF
C1 = 1 μF is effective for the overmodulation
characteristics.
When the PLL is locked, the signal passes via the
path marked A in the figure, and when PLL is
unlocked and in weak signal, the signal passes via
the path marked B in the figure. The PLL loop gain
can thus be switched in this manner.
Pin 7 is a VCO automatic control FLL filter pin.
Since it operates always on a small current, using a
larger capacitance results in a slower response.
Normally, a capacitance between 0.47 μF and 1 μF
is used.
Moreover, the control range for this pin is between
about 3 V to 4.7 V. Since this range is determined
when adjusting the VCO tank circuit, set the design
center of L and C of VCO so that the voltage of pin
7 is 3.6 V.
6
7
APC FILTER
FLL FILTER
Therefore, the peak gain of the EQ amplifier is
determined by Av = 1 + R/Z.
However, note that the LA75505M being an IC with
V
CC
= 5 V, setting too large an amplitude causes
distortion in the V
CC
side. Use so that the white
level is 4 V or less.
This is the VCO tank circuit for the PLL detector.
Use a tuning capacitance of 24 pF.
For the L and C specifications, use IF45.75 MHz
specifications within ±1.5%, and 58.75 MHz
specifications within ±1%. Also, design the L and C
values so that the voltage of pin 7 is 3.6 V when
PLL is locked while using the IF center frequency.
8
9
VCO COIL
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