參數(shù)資料
型號： LAMXO640C-3TN144E
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 18/77頁
文件大?。?/td> 0K
描述： IC FPGA AUTO 640LUTS 144TQFP
標(biāo)準(zhǔn)包裝： 60
系列： LA-MachXO
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 4.9ns
電壓電源 - 內(nèi)部： 1.71 V ~ 3.465 V
宏單元數(shù)： 320
輸入/輸出數(shù)： 113
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤
其它名稱： 220-1640
LAMXO640C-3TN144E-ND
2-22
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
Device Conguration
All LA-MachXO devices contain a test access port that can be used for device conguration and programming.
The non-volatile memory in the LA-MachXO can be congured in two different modes:
In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by
BSCAN registers.
In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode
while reprogramming takes place.
The SRAM conguration memory can be congured in three different ways:
At power-up via the on-chip non-volatile memory.
After a refresh command is issued via the IEEE 1149.1 port.
In IEEE 1532 mode via the IEEE 1149.1 port.
Figure 2-22 provides a pictorial representation of the different programming modes available in the LA-MachXO
devices. On power-up, the SRAM is ready to be congured with IEEE 1149.1 serial TAP port using IEEE 1532 pro-
tocols.
Leave Alone I/O
When using IEEE 1532 mode for non-volatile memory programming, SRAM conguration, or issuing a refresh
command, users may specify I/Os as high, low, tristated or held at current value. This provides excellent exibility
for implementing systems where reconguration or reprogramming occurs on-the-y.
TransFR (Transparent Field Reconguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the eld without interrupting
system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-
ruption During Conguration Using TransFR Technology, for details.
Security
The LA-MachXO automotive devices contain security bits that, when set, prevent the readback of the SRAM con-
guration and non-volatile memory spaces. Once set, the only way to clear the security bits is to erase the memory
space.
For more information on device conguration, please see details of additional technical documentation at the end
of this data sheet.
AEC-Q100 Tested and Qualied
The Automotive Electronics Council (AEC) consists of two committees: the Quality Systems Committee and the
Component Technical Committee. These committees are composed of representatives from sustaining and other
associate members. The AEC Component Technical Committee is the standardization body for establishing stan-
dards for reliable, high quality electronic components. In particular, the AEC-Q100 specication “Stress Test for
Qualication for Integrated Circuits” denes qualication and re-qualication requirements for electronic compo-
nents. Components meeting these specications are suitable for use in the harsh automotive environment without
additional component-level qualication testing. Lattice's LA-ispMACH 4000V and LA-MachXO devices completed
and passed the requirements of the AEC-Q100 specication.
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LAMXO640E-3FTN256E 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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LAMXO640LUTSC-3FTN256E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet
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