參數(shù)資料
型號： LAN83C175
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： Ethernet CARDBUS Integrated Controller With Modem Support
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝： 28 X 28 MM, 1.40 MM HEIGHT, TQFP-208
文件頁數(shù)： 40/92頁
文件大?。?/td> 299K
代理商： LAN83C175
40
manually (by writing to this register) does not
effect the TXUGO bit.
7 - Transmit queue empty - set when NIC
reads a transmit descriptor that is still owned
by the host. This interrupt is cleared
automatically when the TXQUEUED bit in the
command register is set. Clearing this
interrupt manually (by writing to this register)
does not effect the TXQUEUED bit.
6 - TCC: Transmit chain complete - set when
the complete transmit chain has been
processed.
5 - TXC: Transmit complete - set when a
packet has been successfully transmitted or
aborted and the IAF bit is set for that frame.
4 - RXE: Receive error - set when a CRC error
occurs and Monitor mode is off.
3 - OVW: Receive buffer overflow warning -
set when a frame is received and local receive
buffer space is full.
2 - RQE: Receive queue empty - set when NIC
reads a receive descriptor that is still owned
by the host. This interrupt is cleared
automatically when the RXQUEUED bit in the
command register is set. Clearing this
interrupt manually (by writing to this register)
does not effect the RXQUEUED bit.
1 - HCC: Header copy complete - set when
receive frame header has been copied into
host memory.
0 - RCC: Receive copy complete - set when
receive frame has been copied into host
memory.
08 - INTERRUPT MASK
Reset Value: 000000000000000
This register is used to enable certain interrupt
sources selectively. Bits that are 1 allow the
corresponding interrupt to cause an interrupt
request. Bits that are 0 block their interrupt
sources.
31 through 15: Unused.
14 through 0: Interrupt enables.
0C - GENERAL CONTROL
Reset Value: 000000100000000
31 through 15: Unused.
14 - RESET PHY: This bit is or'ed with the
CardBus nRST input to generate the nPHYRST
output for the physical layer device.
13 and 12 - SOFT[1:0]: These two read/write bits
are provided for use by the software driver.
They do not affect hardware operation.
11 through 10 - MEMORY READ CONTROL:
These bits control which CardBus command the
transmit DMA will use when bursting data over the
CardBus bus. When bit 11 is set, the transmit
DMA will use the CardBus "memory read line"
command. When bit 10 is set, the transmit DMA
will use the CardBus "memory read multiple"
command. When neither bit is set the transmit
DMA will use the CardBus "memory read"
command. Use of "memory read multiple" or
"memory read line" may enhance performance
on some machines.
9 and 8 - RECEIVE FIFO THRESHOLD: Controls
the level at which the CardBus burst state
machine begins to empty the receive FIFO.
Default is 1/2 full. D9 = THR_SEL[1], D8 =
THR_SEL[0].
相關PDF資料
PDF描述
LAN83C180 10/100 FAST ETHERNET PHY TRANSCEIVER
LAN83C185 HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
LAN83C183-JD FAST ETHERNET PHYSICAL LAYER DEVICE
LAN83C180TQFP 10/100 FAST ETHERNET PHY TRANSCEIVER
LAN83C183 FAST ETHERNET PHYSICAL LAYER DEVICE
相關代理商/技術參數(shù)
參數(shù)描述
LAN83C175TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMC Corporation of America 功能描述:83C175TQFP 制造商:SMSC 功能描述:
LAN83C175TQFP WAF 制造商:SMSC 功能描述:
LAN83C180 制造商:SMSC 制造商全稱:SMSC 功能描述:10/100 FAST ETHERNET PHY TRANSCEIVER
LAN83C180_01 制造商:SMSC 制造商全稱:SMSC 功能描述:10/100 Fast Ethernet PHY Transceiver
LAN83C180TQFP 制造商:SMSC 制造商全稱:SMSC 功能描述:10/100 Fast Ethernet PHY Transceiver
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*