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參數(shù)資料
| 型號： | LAN83C185-JD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 166K |
| 代理商： | LAN83C185-JD |
SMSC DS – LAN83C180
Page 13
Rev. 08/24/2001
MANAGEMENT
MAC Access to PHY Management Registers
The interface to these registers is via the MDC and MDIO signals. The address of the LAN83C180 is
specified by the PA<4:0> static inputs. The MD command is issued by the MAC and can be read or write:
COMMAND
READ
PREAMBLE
32 Bits of 1
START
DATA
01b
OP
CODE
10b
PHY
ADDRESS
5 Bits
REG
NUMBER
5 Bits
TA
Z0b
DATA
16 bit from
PHY
16 bit from
MAC
WRITE
32 Bits of 1
01b
01b
5 Bits
5 Bits
10b
RESISTER SET
The following register set is implemented in the LAN83C180 device. Each of the registers is accessible to the MAC
at the specified offset. The bit types in the bit description tables follow the following convention:
SC = Self clear
RO = Read only
RW = Read or write
LL = Latch low until register read
LH = Latch high until register read
Res = Reserved
Reg 0 - Control Register
BIT
15
BIT NAME
Reset
DESCRIPTION
DEFAULT
0
TYPE
RW
SC
RW
1 = PHY reset
0 = Normal operation
1 = Loopback mode active
0 = Normal operation
1 = 100 Mbps
0 = 10 Mbps
1 = Enable ANEG process
0 = Disable ANEG process
1 = Power down active
0 = Normal operation
1 = Isolation in process
0 = Normal operation
1 = Restart the ANEG process
0 = Normal operation
1= Full Duplex mode
0 = Half duplex mode
1 = Collision test active
0 = Normal operation
Write as 0; ignore on read
14
Loopback
0
13
Speed Selection
1
RW
12
ANEG Enable
1
RW
11
Power Down
0
RW
10
Isolation
0
RW
9
Restart ANEG
0
RW
SC
RW
8
Duplex Selection
1
7
Collision Test
0
RW
6:0
Reserved
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