參數(shù)資料
型號： LB1876(36SOP)
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 10/14頁
文件大小： 120K
代理商： LB1876(36SOP)
No. 6201-10/14
LB1876
Continued from preceding page.
Pin No.
Symbol
Description
Equivalent circuit
FG Schmitt output
24
FGS
VREG
24
VREG
25
Continued on next page.
Phase lock detection output
Turns on (goes low) when phase lock is
detected.
25
LD
VREG
22k
2k
26
Start/stop control
Low: 0 to 1.5 V
High: 3.5 V to VREG
Hysteresis: About 0.5 V
Apply a low level to start; this pin goes high
when open.
26
S/S
VREG
22k
2k
27
Clock input
Low: 0 to 1.5 V
High: 3.5 V to VREG
Hysteresis: About 0.5 V
fCLK = 10 kHz maximum
If there is noise on the clock signal, remove
that noise with a capacitor.
27
CLK
31
VCC
Stabilized power supply output (5 V output)
Insert a capacitor between this pin and
ground for stabilization. (About 0.1 μF.)
31
VREG
Power supply
Insert a capacitor between this pin and ground
to prevent noise from entering the IC. (Use a
value of 20 or 30 μF or higher.)
30
V
CC
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