參數(shù)資料
型號： LC07410LG
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA40
封裝： 4.40 X 3.60 MM, FLGA-40
文件頁數(shù)： 21/36頁
文件大?。?/td> 367K
代理商： LC07410LG
LC07410LG
No.A1345-28/36
Register Table
ADRS (Address): displayed in hexadecimal notation,
Init (initial value): displayed in hexadecimal notation
Register bits indicated by "0" must be set to 0.
Registers indicated with a gray background are for IC testing and their initial values are fixed.
All registers (addresses: 00 to 25h) must be loaded with write data (including test registers).
Register Data D[7:0]
Functions
ADRS
[7:0]
Init
7
6
5
4
3
2
1
0
PM1
00h
MIC_PDX
MIC_PWR_PDX
PGA_PDX
ADC_PDX
DAC_PDX
SEL_PDX
LO_PDX
SP_PDX
PM2
01h
00h
SYNC_CLR
0
VREF_BIAS[1]
VREF_BIAS[0]
0
PLL_PDX
REG_PDX
VD_PDX
MIC
02h
10h
0
MIC_GAIN[1]
MIC_GAIN[0]
0
ALC1
03h
12h
0
ALC_VAL[2]
ALC_VAL[1]
ALC_VAL[0]
0
ALC_FA1[2]
ALC_FA1[1]
ALC_FA1[0]
ALC2
04h
24h
0
ALC_THA[2]
ALC_THA[1]
ALC_THA[0]
0
ALC_FA2[2]
ALC_FA2[1]
ALC_FA2[0]
ALC3
05h
34h
0
ALC_THR1[2]
ALC_THR1[1]
ALC_THR1[0]
0
ALC_FR1[2]
ALC_FR1[1]
ALC_FR1[0]
ALC4
06h
34h
0
ALC_THR2[2]
ALC_THR2[1]
ALC_THR2[0]
0
ALC_FR2[2]
ALC_FR2[1]
ALC_FR2[0]
ALC5
07h
04h
0
ALC_FR3[2]
ALC_FR3[1]
ALC_FR3[0]
ALC6
08h
56h
ALC_FULLEN
ALC_ZCD
ALC_ZCDTM[1]
ALC_ZCDTM[0]
ALC_TLIM[1]
ALC_TLIM[0]
ALC_RWT[1]
ALC_RWT[0]
ALC7
09h
49h
ALC_NGEN
ALC_NGTH[2]
ALC_NGTH[1]
ALC_NGTH[0]
ALC_NGDT[1]
ALC_NGDT[0]
ALC_NGRT[1]
ALC_NGRT[0]
ALC8
0Ah
0
1
0
1
0
ALC9
0Bh
0Eh
0
ALC_VMAX[5]
ALC_VMAX[4]
ALC_VMAX[3]
ALC_VMAX[2]
ALC_VMAX[1]
ALC_VMAX[0]
ALC10
0Ch
0Eh
0
ALC_GAIN[5]
ALC_GAIN[4]
ALC_GAIN[3]
ALC_GAIN[2]
ALC_GAIN[1]
ALC_GAIN[0]
CODEC1
0Dh
02h
FILTER2
FILTER1
WIND_CUT[1]
WIND_CUT[0]
AD_MUTE
FBCLK
REC_ALC
PB_ALC
CODEC2
0Eh
00h
0
ADF_MASTER
ADF_DAC_INV
ADF_ADC_INV
ADF_MODE[1]
ADF_MODE[0]
CODEC3
0Fh
00h
0
ADF_LB
0
SEL_USE_DSP
0
EVR1
10h
80h
EVR_MUTE
EVR_GAIN[6]
EVR_GAIN[5]
EVR_GAIN[4]
EVR_GAIN[3]
EVR_GAIN[2]
EVR_GAIN[1]
EVR_GAIN[0]
EVR2
11h
54h
0
EVR_VOLZCD
EVR_ZCDTM[1] EVR_ZCDTM[0]
0
EVR_SOFTSW
EVR_VOLTM[1]
EVR_VOLTM[0]
LINE/SEL
12h
E1h
LO_MUTE
LO_VREFSW
LO_GAIN[1]
LO_GAIN[0]
0
SEL_GAIN
SEL_IN[1]
SEL_IN[0]
SPK1
13h
38h
BPMODE[1]
BPMODE[0]
BPVOL[1]
BPVOL[0]
SP_IDL[1]
SP_IDL[0]
SP_BIAS[1]
SP_BIAS[0]
SPK2/VIDEO
14h
41h
SP_OUT_EN
SP_TSD_EN
0
VD_GAIN
VD_DCTL[3]
VD_DCTL[2]
VD_DCTL[1]
VD_DCTL[0]
FS
15h
08h
0
FS[3]
FS[2]
FS[1]
FS[0]
PLL1_1
16h
00h
0
SEL_MCLKO[1]
SEL_MCLKO[0]
0
PLL_DIV1[8]
PLL1_2
17h
7Dh
PLL_DIV1[7]
PLL_DIV1[6]
PLL_DIV1[5]
PLL_DIV1[4]
PLL_DIV1[3]
PLL_DIV1[2]
PLL_DIV1[1]
PLL_DIV1[0]
PLL2_1
18h
00h
0
PLL_DIV2[8]
PLL2_2
19h
80h
PLL_DIV2[7]
PLL_DIV2[6]
PLL_DIV2[5]
PLL_DIV2[4]
PLL_DIV2[3]
PLL_DIV2[2]
PLL_DIV2[1]
PLL_DIV2[0]
PLL3
1Ah
00h
0
PLL_FCKI[1]
PLL_FCKI[0]
0
PLL_DIV3[1]
PLL_DIV3[0]
FILTER1_A1
1Bh
00h
A1[15]
A1[14]
A1[13]
A1[12]
A1[11]
A1[10]
A1[9]
A1[8]
FILTER1_A1
1Ch
00h
A1[7]
A1[6]
A1[5]
A1[4]
A1[3]
A1[2]
A1[1]
A1[0]
FILTER1_A2
1Dh
00h
A2[15]
A2[14]
A2[13]
A2[12]
A2[11]
A2[10]
A2[9]
A2[8]
FILTER1_A2
1Eh
00h
A2[7]
A2[6]
A2[5]
A2[4]
A2[3]
A2[2]
A2[1]
A2[0]
FILTER1_B0
1Fh
40h
B0[15]
B0[14]
B0[13]
B0[12]
B0[11]
B0[10]
B0[9]
B0[8]
FILTER1_B0
20h
00h
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
FILTER1_B1
21h
00h
B1[15]
B1[14]
B1[13]
B1[12]
B1[11]
B1[10]
B1[9]
B1[8]
FILTER1_B1
22h
00h
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
FILTER1_B2
23h
00h
B2[15]
B2[14]
B2[13]
B2[12]
B2[11]
B2[10]
B2[9]
B2[8]
FILTER1_B2
24h
00h
B2[7]
B2[6]
B2[5]
B2[4]
B2[3]
B2[2]
B2[1]
B2[0]
FILTER2_A1
25h
00h
A1[15]
A1[14]
A1[13]
A1[12]
A1[11]
A1[10]
A1[9]
A1[8]
FILTER2_A1
26h
00h
A1[7]
A1[6]
A1[5]
A1[4]
A1[3]
A1[2]
A1[1]
A1[0]
FILTER1_A2
27h
00h
A2[15]
A2[14]
A2[13]
A2[12]
A2[11]
A2[10]
A2[9]
A2[8]
FILTER1_A2
28h
00h
A2[7]
A2[6]
A2[5]
A2[4]
A2[3]
A2[2]
A2[1]
A2[0]
Continued on next page
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