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參數(shù)資料
| 型號(hào)： | LC07410LG |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA40 |
| 封裝： | 4.40 X 3.60 MM, FLGA-40 |
| 文件頁(yè)數(shù)： | 9/22頁(yè) |
| 文件大小： | 473K |
| 代理商： | LC07410LG |
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LC07410LG
No.A1345-17/36
Relation Between Output level and Recovery Speed (FR,THR)
FR2
FR1
FR3
ALC VAL
THR2
THR1
Signal after
ADC
FR value is shown by inclination (FS/s) of the shape of recovery waves. (FS = Full Scale = 0dBFS)
Description of ALC/Limiter (automatic level control) operation
Note: Whatever is contained inside the parentheses “ ” is applicable in the PB-ALC mode.
The amplifier gain “digital volume value” of the PGA (programmable gain amplifier) is automatically adjusted so that
the A/D converter output audio level “digital volume output” is set to the ALC value “ALC_VAL [2:0]”. The PGA
“digital volume” gain can be varied in the -14dB to +34dB range. The maximum value “ALC_VMAX [5:0]” can be set
in this variable range.
ALC settings
Power-saving function
When [PGA_PDX] is 0, the ALC circuit and PGA circuit are set to power down mode.
Manual function (ALC OFF)
At REC_ALC = PB_ALC = 0, it become manual mode.
PGA gain is fixed by value of ALC_GAIN [5:0]
Digital volume value is fixed by EVR_GAIN [6:0]
System operation
ALC is performed by feeding back the A/D converter “digital volume” data. Accordingly, configure the settings
as shown in the table below in order for the ALC functions to be activated.
(1) Attack operations
When the ADC “digital volume” output exceeds the ALC limiter level, ALC_VAL[2:0], the PGA gain “digital
volume value” is lowered. When the rate of gain attenuation is ALC_THA[2:0] or more, ALC_FA1[1:0] results, but
when the value is less than ALC_THA[2:0], ALC_FA2[1:0] results.
When zero-cross detection ALC_ZCD is set to 1, the gain attenuation from zero-cross to zero-cross is limited by the
limit value ALC_TLIM[1:0].
Mode
Resister
REC-ALC
PB-ALC
PGA_PDX
1
0
ADC_PDX
1
x
DAC_PDX
x
1
REC_ALC
1
0
PB_ALC
0
1
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