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參數(shù)資料
| 型號： | LC3564RT-10LV |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 64K (8192 words x 8 bits) SRAM |
| 中文描述： | 64K的（8192字× 8位）的SRAM |
| 文件頁數(shù)： | 9/10頁 |
| 文件大小： | 442K |
| 代理商： | LC3564RT-10LV |
LC3564RM,RT-10LV/12LV/15LV
No. 4484—9/10
Write Cycle 2 (CE1 write): Note 6
Write Cycle 3 (CE2 write): Note 6
Note: 1. We should be held high level during the read cycle
2. Do not apply external signals that are out-of-phase with D
OUT
3. t
WP
is a period when CE1 and WE are LOW and CE2 is HIGH. It is measured from when WE goes low level to when either CE1 and WE go HIGH or CE2 goes
LOW, whichever occurs first.
4. t
CW1
and t
CW2
are periods when CE1 and WE are LOW and CE2 is HIGH. They are measured from when CE1 goes LOW and CE2 goes HIGH, respectively,
to when either CE1 and WE go HIGH or CE2 goes LOW, whichever occurs first.
5. The outputs D
OUT1
to D
OUT8
are in a high-impedance state when OE is HIGH, CE1 is HIGH, CE2 is LOW and WE is LOW.
6. During the write cycle, OE is V
IH
or V
IL
.
7. D
OUT
has the same phase as the write data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC3564RT-12LV | 64K (8192 words x 8 bits) SRAM |
| LC3564RT-15LV | 64K (8192 words x 8 bits) SRAM |
| LC3564RM-12LV | |
| LC3564RM | ECONOLINE: RSZ/P - 1kVDC |
| LC3564ST-10 | 64K (8192 words x 8 bits) SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC3564RT-12LV | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:64K (8192 words x 8 bits) SRAM |
| LC3564RT-15LV | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:64K (8192 words x 8 bits) SRAM |
| LC3564S | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:64K (8192 words x 8 bits) SRAM |
| LC3564S_SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC3564S-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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