參數(shù)資料
型號： LC4256V-75F256AC
文件頁數(shù)： 19/57頁
文件大?。?/td> 1078K
代理商： LC4256V-75F256AC
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
19
ispMACH 4000V/B/C External Switching Characteristics (Cont.)
Over Recommended Operating Conditions
Parameter
t
PD
Description
1, 2, 3
-5
-75
-10
5
Units
ns
ns
Min.
—
—
Max.
5.0
5.5
Min.
—
—
Max.
7.5
8.0
Min.
—
—
Max.
10.0
10.5
5-PT bypass combinatorial propagation delay
20-PT combinatorial propagation delay through macro-
cell
GLB register setup time before clock
GLB register setup time before clock with
T-type register
GLB register setup time before clock, input register path
GLB register setup time before clock with zero hold
GLB register hold time after clock
GLB register hold time after clock with
T-type register
GLB register hold time after clock, input register path
GLB register hold time after clock, input register path with
zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output enable/disable
Input to output global product term output enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low transparent) or high (for
high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
Clock frequency with external feedback,
[1/ (t
S
+ t
CO
)]
t
PD_MC
t
S
3.0
3.2
—
—
4.5
4.7
—
—
5.5
5.5
—
—
ns
ns
t
ST
t
SIR
t
SIRZ
t
H
1.2
2.2
0.0
0.0
—
—
—
—
1.7
2.7
0.0
0.0
—
—
—
—
1.7
2.7
0.0
0.0
—
—
—
—
ns
ns
ns
ns
t
HT
t
HIR
1.0
0.0
—
—
1.0
0.0
—
—
1.0
0.0
—
—
ns
t
HIRZ
ns
t
CO
t
R
t
RW
t
PTOE/DIS
t
GPTOE/DIS
t
GOE/DIS
t
CW
—
—
2.0
—
—
—
2.2
2.2
3.40
6.30
—
7.00
9.00
5.00
—
—
—
—
4.0
—
—
—
3.3
3.3
4.5
9.0
—
9.0
10.3
7.0
—
—
—
—
4.0
—
—
—
4.0
4.0
6.0
10.5
—
10.5
12.0
8.0
—
—
ns
ns
ns
ns
ns
ns
ns
t
GW
ns
t
WIR
f
MAX
2.2
227
156
—
—
—
3.3
168
111
—
—
—
4.0
125
86
—
—
—
ns
MHz
4
f
MAX
(Ext.)
MHz
Timing v.3.1
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
5. Only available in industrial grade.
相關PDF資料
PDF描述
LC4256V-75F256AI
LC4256V-75T100C
LC4256V-75T100I
LC4256V-75T176C
LC4256V-75T176I
相關代理商/技術參數(shù)
參數(shù)描述
LC4256V-75F256AC1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-75F256AI 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4256V-75F256AI1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-75F256B-10I 制造商:Lattice Semiconductor Corporation 功能描述:
LC4256V-75F256BC 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 160 I/O RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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