參數資料
型號: LC5256MB-5F256C
廠商: Lattice Semiconductor Corporation
文件頁數: 57/99頁
文件大小: 0K
描述: IC XPLD 256MC 5NS 256FPBGA
標準包裝: 90
系列: ispXPLD® 5000MB
可編程類型: 系統內可編程
最大延遲時間 tpd(1): 5.0ns
電壓電源 - 內部: 2.3 V ~ 2.7 V
邏輯元件/邏輯塊數目: 8
宏單元數: 256
輸入/輸出數: 141
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應商設備封裝: 256-FPBGA(17x17)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
56
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs
3
51N
F2
E1
F1
F3
B8
3
51P
F0
E0
F0
F1
C8
0
52N
G30
G31
H31
G31
B7
0
52P
G28
G30
H30
G29
A7
-
GND
---
NC
0
53N
G26
G29
H29
G27
D7
0
53P
G24
G28
H28
G25
C7
0
54N
G22
G27
H27
G23
B6
-
VCCO0
-
VCCO0
0
54P
G21
G26
H26
-
E7
-
GND (Bank 0)
-
GND (Bank 0)
0
55N
G20
G25
H25
-
E6
0
55P
G18
G24
H24
G19
A6
0
56N
G16/VREF0
G3
H3
G17
A5
0
56P
G14
G2
H2
G15
A4
0
57N
G12
G23
H23
G13
B5
0
57P
G10
G22
H22
G11
A3
0
58N
G8
G21
H21
G9
B4
0
58P
G6
G20
H20
G7
B3
0
59N
G5
G19
H19
-
C5
0
59P
G4
G18
H18
-
C6
0
60N
G2
G1
H1
G3
D5
0
60P
G0
H0
G1
D6
-
VCCO0
-
VCCO0
-
GND (Bank 0)
-
GND (Bank 0)
ispXPLD 5256MX Logic Signal Connections (Continued)
sysIO Bank
LVDS Pair
Primary Macrocell/
Function
Alternate Outputs
Alternate Input
256 fpBGA
Ball Number
Macrocell 1
Macrocell 2
SELECT
DEVICES
DISCONTINUED
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