參數(shù)資料
型號: LC5256MV-5FN256I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 44/99頁
文件大?。?/td> 0K
描述: IC CPLD 256MACROCELLS 256FPBGA
標準包裝: 90
系列: ispXPLD® 5000MV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 5.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 8
宏單元數(shù): 256
輸入/輸出數(shù): 141
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
45
Boundary Scan Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min
Max
Units
tBTCP
TCK [BSCAN] clock pulse width
40
ns
tBTCPH
TCK [BSCAN] clock pulse width high
20
ns
tBTCPL
TCK [BSCAN] clock pulse width low
20
ns
tBTS
TCK [BSCAN] setup time
8
ns
tBTH
TCK [BSCAN] hold time
10
ns
tBTRF
TCK [BSCAN] rise/fall time
50
mV/ns
tBTCO
TAP controller falling edge of clock to valid output
10
ns
tBTCODIS
TAP controller falling edge of clock to valid disable
10
ns
tBTCOEN
TAP controller falling edge of clock to valid enable
10
ns
tBTCRS
BSCAN test capture register setup time
8
ns
tBTCRH
BSCAN test capture register hold time
10
ns
tBUTCO
BSCAN test update register, falling edge of clock to valid output
25
ns
tBTUODIS
BSCAN test update register, falling edge of clock to valid disable
25
ns
tBTUPOEN
BSCAN test update register, falling edge of clock to valid enable
25
ns
SELECT
DEVICES
DISCONTINUED
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