參數(shù)資料
型號: LC5256MV-75F256I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 3/99頁
文件大?。?/td> 0K
描述: IC XPLD 256MC 7.5NS 256FPBGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPLD® 5000MV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 8
宏單元數(shù): 256
輸入/輸出數(shù): 141
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
7
Figure 6. Dual-OR PT Sharing Array
Product Term Sharing Array
The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array (Expandable PTSA OR) and
32 outputs directly to the macrocells. Each output is the OR term of any combination of the seven Expandable
PTSA OR terms connected to that output. Every Nth macrocell is connected to N-3, N-2, N-1, N, N+1, N+2 and
N+3 PTSA OR terms via a programmable connection. This wraps around the logic, for example, Macrocell 0 gets
its logic from 29, 30, 31, 0, 1, 2, 3. The Expandable PTSA OR used in conjunction with the PTSA allows wide func-
tions to be implemented easily and efficiently. Without using the Expandable PTSA OR capability, the greatest
number of product terms that can be included in a single function with one pass of delay is 35. Up to 160 product
terms can be included in a single function through the use of the expandable PTSA OR capability. Figure 7 shows
the graphical representation of the PTSA.
Figure 7. Product Term Sharing Array (PTSA)
From
n-7
Carry
In
Carry
Out
To
n+7
From PT0
From PT1
From PT2
From PT3
From PT4
PTSA Bypass
To Macrocell
To I/O Block
To Macrocell
To PTSA
PT OE
PT Clock
PT Preset
PT Reset
N
PTSA OR 0
PTSA OR 1
PTSA OR 2
PTSA OR 3
PTSA OR 29
PTSA OR 30
PTSA OR 31
Macrocell 0
Macrocell 1
Macrocell 2
Macrocell 29
Macrocell 30
Macrocell 31
SELECT
DEVICES
DISCONTINUED
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