參數(shù)資料
型號： LC5512MB-45F256C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 45/99頁
文件大?。?/td> 0K
描述： IC XPLD 512MC 4.5NS 256FPBGA
標(biāo)準(zhǔn)包裝： 90
系列： ispXPLD® 5000MB
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 4.5ns
電壓電源 - 內(nèi)部： 2.3 V ~ 2.7 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 512
輸入/輸出數(shù)： 193
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FPBGA（17x17）
包裝： 托盤
www.latticesemi.com
1
5kmx_12.4
ispXPLD 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD Family
February 2010
Data Sheet
TM
2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Features
Flexible Multi-Function Block (MFB)
Architecture
SuperWIDE logic (up to 136 inputs)
Arithmetic capability
Single- or Dual-port SRAM
FIFO
Ternary CAM
sysCLOCK PLL Timing Control
Multiply and divide between 1 and 32
Clock shifting capability
External feedback capability
sysIO Interfaces
LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
– Open drain operation
SSTL 2, 3 (I & II)
HSTL (I, III, IV)
PCI 3.3
GTL+
LVDS
LVPECL
LVTTL
Expanded In-System Programmability (ispXP)
Instant-on capability
Single chip convenience
In-System Programmable via IEEE 1532
Interface
Infinitely reconfigurable via IEEE 1532 or sys-
CONFIG microprocessor interface
Design security
High Speed Operation
4.0ns pin-to-pin delays, 300MHz fMAX
Deterministic timing
Low Power Consumption
Typical static power: 20 to 50mA (1.8V),
30 to 60mA (2.5/3.3V)
1.8V core for low dynamic power
Easy System Integration
3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
IEEE 1149.1 interface for boundary scan testing
sysIO quick configuration
Density migration
Multiple density and package options
PQFP and fine pitch BGA packaging
Lead-free package options
Table 1. ispXPLD 5000MX Family Selection Guide
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX ispXPLD 51024MX
Macrocells
256
512
768
1,024
Multi-Function Blocks
8
16
24
32
Maximum RAM Bits
128K
256K
384K
512K
Maximum CAM Bits
48K
96K
144K
192K
sysCLOCK PLLs
2
tPD (Propagation Delay)
4.0ns
4.5ns
5.0ns
5.2ns
tS (Register Set-up Time)
2.2ns
2.8ns
3.0ns
tCO (Register Clock to Out Time)
2.8ns
3.0ns
3.2ns
3.7ns
fMAX (Maximum Operating Frequency)
300MHz
275MHz
250MHz
Functional Gates
75K
150K
225K
300K
I/Os
141
149/193/253
193/317
317/381
Packages
256 fpBGA
208 PQFP
256 fpBGA
484 fpBGA
256 fpBGA
484 fpBGA
672 fpBGA
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