參數(shù)資料
型號(hào): LC5512MC-45F484C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述: EE PLD, 5.7 ns, PBGA484
封裝: FPBGA-484
文件頁(yè)數(shù): 39/92頁(yè)
文件大小: 378K
代理商: LC5512MC-45F484C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
39
t
DPCEBS
Clock Enable B
Setup before Clock
B Time
Clock Enable Hold
B after Clock B
Time
Address B Setup
before Clock B Time
Address B Hold
time after Clock B
Time
R/W B Setup before
Clock B Time
R/W B Hold time
after Clock B Time
Write Data B Setup
before Clock B Time
Write Data B Hold
after Clock B Time
Read Clock A to
Output Delay
Read Clock B to
Output Delay
Opposite Clock
Cycle Delay
Reset to RAM
Output Delay
Reset Recovery
Time
Reset Pulse Width
2.33
2.33
2.33
2.33
3.03
ns
t
DPCEBH
-2.95
-2.95
-2.95
-2.95
-2.27
ns
t
DPADDBS
-0.27
-0.27
-0.27
-0.27
-0.21
ns
t
DPADDBH
-0.01
-0.01
-0.01
-0.01
-0.01
ns
t
DPRWBS
-0.27
-0.27
-0.27
-0.27
-0.21
ns
t
DPRWBH
-0.01
-0.01
-0.01
-0.01
-0.01
ns
t
DPDATABS
-0.27
-0.27
-0.27
-0.27
-0.21
ns
t
DPDATABH
-0.01
-0.01
-0.01
-0.01
-0.01
ns
t
DPRCLKAO
5.97
5.92
5.86
5.65
9.86
ns
t
DPRCLKBO
5.16
5.16
5.16
5.16
6.71
ns
t
DPCLKSKEW
1.40
1.40
1.40
1.40
1.83
ns
t
DPRSTO
3.30
3.30
3.30
3.30
4.29
ns
t
DPRSTR
1.20
1.20
1.20
1.20
1.56
ns
t
DPRSTPW
0.14
0.14
0.14
0.14
0.19
ns
1. The PT-delay to clock of RAM/FIFO/CAM should be t
BCLK
instead of t
PTCLK.
2. The PT-delay to set/reset of RAM/FIFO/CAM should be t
BSR
instead of t
PTSR.
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Base
Parameter
-4
-45
-5
-52
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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