- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19711 > LC5512MC-75QN208I (Lattice Semiconductor Corporation)IC XPLD 512MC 7.5NS 208PQFP PDF資料下載
參數(shù)資料
| 型號： | LC5512MC-75QN208I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 17/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XPLD 512MC 7.5NS 208PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | ispXPLD® 5000MC |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 1.65 V ~ 1.95 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 512 |
| 輸入/輸出數(shù)： | 149 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
20
Programmable Slew Rate
The slew rate of outputs is carefully controlled. When outputs are configured as LVCMOS the devices support two
slew rates. This allows system noise and performance to be balanced in a design.
Programmable Bus-Maintenance
All general-purpose inputs have programmable bus maintenance circuitry. These are intended to maintain a valid
logic level into a device when driving devices go into the tri-state mode. Four options are available for users: pull-
up, pull-down, bus-keeper, or nothing.
Expanded In-System Programmability (ispXP)
The ispXPLD 5000MX family utilizes a combination of EEPROM non-volatile cells and SRAM technology to deliver
a logic solution that provides “instant-on” at power-up, a convenient single chip solution, and the capability for infi-
nite reconfiguration. A non-volatile array distributed within the device stores the device configuration. At power-up
this information is transferred in a massively parallel fashion into SRAM bits that control the operation of the device.
Figure 18 shows the different ports and modes that are used in the configuration and programming of the ispXPLD
5000MX devices.
Figure 18. ispXP Block Diagram
IEEE 1532 ISP
In-system programming of devices provides a number of significant benefits including rapid prototyping, lower
inventory levels, higher quality and the ability to make in-field modifications. All ispXPLD 5000MX devices provide
in-system programmability through their Boundary Scan Test Access Port. This capability has been implemented in
a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the
communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined inter-
face.
The IEEE1532 programming interface allows programming of either the non-volatile array or reconfiguration of the
SRAM bits.
The ispXPLD 5000MX devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispXPLD 5000MX devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
mated test equipment. This equipment can then be used to program ispXPLD 5000MX devices during the testing
of a circuit board.
SRAM
Memory Space
E2CMOS
Memory Space
sysCONFIG Peripheral Port
sysCONFIG
ISP 1149.1 TAP Port
Power-up
Refresh
Programming
in seconds
Download in
microseconds
Configuration
in milliseconds
Port
Mode
Memory Space
ISP
1532
BACKGND
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-B5L-CY-F4 | CONVERTER MOD DC/DC 28V 50W |
| NLCV32T-151K-PF | INDUCTOR POWER 150UH 1210 |
| 180-015-203L021 | CONN DB15 FEML HD SLD CUP NICKEL |
| M5LV-128/104-7VC | IC CPLD 128MC 104I/O 144TQFP |
| HIP1013CB-T | IC CTRLR HOTPLUG DUAL 14-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC5512M-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Board for XPLD5512 PAC1208 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| LC5512MV-45F208C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-45F208I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-45F256C | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 193 I/O RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC5512MV-45F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。