
Continued from preceding page.
No. 4677-22/23
LC66354B, 66356B, 66358B
Mnemonic
Instruction code
Operation
Description
Affected
status bits
Note
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Set to one the bit in port
P (DP
L
) specified by the
immediate data t
1
t
0
.
Clear to zero the bit in port
P (DP
L
) specified by the
immediate data t
1
t
0
.
Take the logical and of P (P
3
to P
0
) and the immediate
data I
3
I
2
I
1
I
0
and output the
result to P (P
3
to P
0
).
Take the logical or of P (P
3
to
P
0
) and the immediate data
I
3
I
2
I
1
I
0
and output the
result to P (P
3
to P
0
).
Write the contents of M2 (HL),
AC into the timer 0 reload
register.
SPB t2
Set port bit
0
0
0
0
1
0
t
1
t
0
1
1
[P (DP
L
), t2]
←
1
RPB t2
Reset port bit
0
0
1
0
1
0
t
1
t
0
1
1
[P (DP
L
), t2]
←
0
ZF
And port with
immediate data
then output
ANDPDR
i4, p4
1
I
3
1
I
2
0
I
1
0
I
0
0
1
0
1
2
2
P (P
3
to P
0
)
←
[P (P
3
to 0)] I
3 to 0
ZF
P
3
P
2
P
1
P
0
Or port with
immediate data
then output
ORPDR
i4, p4
1
I
3
1
I
2
0
I
1
0
I
0
0
1
0
0
2
2
P (P
3
to P
0
)
←
[P (P
3
to 0)] I
3 to 0
ZF
P
3
P
2
P
1
P
0
TIMER0
←
[M2 (HL)],
(AC)
WTTM0
Write timer 0
1
1
0
0
1
0
1
0
1
2
1
1
1
1
0
1
0
1
1
0
1
1
1
0
1
0
Write the contents of E, AC
into the timer 1 reload
register A.
WTTM1
Write timer 1
2
2
TIMER1
←
(E), (AC)
M2 (HL), AC
←
(TIMER0)
Read out the contents of the
timer 0 counter into M2 (HL),
AC.
RTIM0
Read timer 0
1
1
0
0
1
0
1
1
1
2
RTIM1
Read timer1
1
1
1
1
0
1
0
1
1
0
1
1
1
0
1
1
2
2
E, AC
←
(TIMER1)
Read out the contents of the
timer 1 counter into E, AC.
START0
Start timer 0
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
0
2
2
Start timer 0 counter
Start the timer 0 counter.
START1
Start timer 1
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
1
2
2
Start timer 1 counter
Start the timer 1 counter.
STOP1
Stop timer 0
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
2
2
Stop timer 0 counter
Stop the timer 0 counter.
STOP1
Stop timer 1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
1
2
2
Stop timer 1 counter
Stop the timer 1 counter.
MSET
Set interrupt
master enable flag
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
2
2
MSE
←
1
Set the interrupt master
enable flag to one.
MRESET
Reset interrupt
master enable flag
1
1
1
0
0
0
0
1
1
0
1
0
0
0
1
0
2
2
MSE
←
0
Clear the interrupt master
enable flag to zero.
EIH i4
Enable interrupt
high
1
0
1
1
0
0
0
1
1
I
3
1
I
3
1
I
3
1
I
3
1
1
1
I
2
1
I
2
1
I
2
1
I
2
1
0
0
I
1
0
I
1
0
I
1
0
I
1
1
1
1
I
0
1
I
0
1
I
0
1
I
0
1
0
2
2
EDIH
←
(EDIH) i4
Set the interrupt enable flag
to one.
EIL i4
Enable interrupt
low
1
0
1
1
0
0
0
0
2
2
EDIL
←
(EDIL) i4
Set the interrupt enable flag
to one.
DIH i4
Disable interrupt
high
1
1
1
0
0
0
0
1
2
2
EDIH
←
(EDIL) i4
Clear the interrupt enable
flag to zero.
ZF
DIL i4
Disable interrupt
low
1
1
1
0
0
0
0
0
2
2
EDIL
←
(EDIL) i4
Clear the interrupt enable
flag to zero.
ZF
WTSP
Write SP
1
1
1
1
0
0
0
1
2
2
SP
←
(E), (AC)
Transfer the contents of E,
AC to SP.
RSP
Read SP
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
2
2
E, AC
←
(SP)
Transfer the contents of SP
to E, AC.
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
HALT
HALT
2
2
HALT
Enter halt mode.
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
HOLD
HOLD
2
2
HOLD
Enter HOLD mode.
I
g
N
b
N
c
I
T
I
S
i
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