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參數(shù)資料
| 型號： | LC7152NM |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 55 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 287K |
| 代理商： | LC7152NM |
Description of Serial Data
No.
Controller/Data
Description
Related Data
(1)
Side-A
programmable
divider data: DA0
to DA15
.
This data sets the side-A programmable divider number. This data is a
binary value in which DA0 is the LSB.
The range of divider values that can be set is 272 to 65,535.
NA = fVCO-A/fref
R0 to R13
(2)
Side-B
programmable
divider data: DB0
to DB15
.
This data sets the side-B programmable divider number. This data is a
binary value in which DB0 is the LSB.
The range of divider values that can be set is 272 to 65,535.
NB = fVCO-B/fref
R0 to R13
(3)
Reference
frequency data: R0
to R13
.
This data sets the reference divider number. This data is a binary value in
which R0 is the LSB.
The range of divider values that can be set is 8 to 16,383.
(Actual divider number) = (setting) x 2
(reference frequency: fref) = (fX’tal: XIN)/(actual divider number)
UL0 Ul1 UE0 UE1
(4)
Output port data:
OA, OB
.
This data determines the output on the general-purpose output port.
OA → OUTA
OB → OUTB
.
Data 0: open; Data 1: low
.
During the power-on reset in the LC7152NM, OA and OB are both ‘‘0’’.
(5)
Input frequency
range switching
data: FA, FB
.
This data switches the input frequency range for the PIA and PIB pins.
(FA → PIA, FB → PIB)
.
In the case of the LC7152KM: Data 1: 55 to 80 MHz (VDD =2.7 Vto3.3 V)
DA0 to DA15
DB0 to DB15
(6)
Standby mode data
:SB
.
This data puts the PLL in standby mode.
.
SB = 1: standby mode (LDB pin: open)
→ Single PLL operation: Side-A operating, side-B stopped
.
SB = 0: standby mode off
→ Dual PLL operation: Side-A operating, side-B operating
.
During the power-on reset in the LC7152NM, SB is ‘‘1’’.
(7)
Unlock detection
data
: UL0, UL1
:UE0,UE1
.
This is the phase error detection threshold data that is used for PLL
lock/unlock discrimination. If the threshold shown in the table is exceeded,
the unlocked state is detected.
unit : μs
(Note) Note that if the data changes in lock state, the PLL will be unlocked
temporarily.
.
The detected phase error (E) signal can be extended by a certain amount
of time and output on the LDA and LDB pins. This data determines the
length of this extension. However, when UL0 = UL1 = 0, the phase error is
not extended, and is output directly.
unit : ms
(*standard value)
Continued on next page.
Data
Supply voltage (VDD)
2.0 to 3.3 V
[0]
1.5 to 23 MHz
[1]
20to55MHz
UL0 UL1
Phase error
detector
threshold
XIN : fXIN [MHz] example
4.0
7.2
8.0
10.24
12.8
00
0
←←←←←
10
±4/fX’tal
±1.00
±0.55
±0.50
±0.39
±0.31
01
±16/fX’tal
±4.00
±2.22
±2.00
±1.56
±1.20
11
±64/fX’tal
±16.00
±8.88
±8.00
±6.25
±5.00
UE0
UE1
Reference
frequency
fref
Reference frequency :
fref [kHz] example
1kHz
5kHz
12.5 kHz
00
4 × (1/fref)
4.0*
0.8
0.32
10
8 × (1/fref)
8.0
1.6
0.64
01
32 × (1/fref)
32.0
6.4*
2.56
11
64 × (1/fref)
64.0
12.8
5.12*
LC7152, 7152M, 7152NM, 7152KM
No.3889-8/13
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